# RUN: llc -mtriple=aarch64-linux-gnu -run-pass=greedy %s -o - | FileCheck %s
# RUN: llc -mtriple=aarch64-linux-gnu -start-before=greedy -stop-after=aarch64-expand-pseudo -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=EXPAND
--- |
; ModuleID = '<stdin>'
source_filename = "<stdin>"
target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
target triple = "aarch64--linux-gnu"
define aarch64_sve_vector_pcs void @spills_fills_stack_id_ppr() #0 { entry: unreachable }
define aarch64_sve_vector_pcs void @spills_fills_stack_id_ppr2() #0 { entry: unreachable }
define aarch64_sve_vector_pcs void @spills_fills_stack_id_ppr2mul2() #0 { entry: unreachable }
define aarch64_sve_vector_pcs void @spills_fills_stack_id_pnr() #1 { entry: unreachable }
define aarch64_sve_vector_pcs void @spills_fills_stack_id_virtreg_pnr() #1 { entry: unreachable }
define aarch64_sve_vector_pcs void @spills_fills_stack_id_virtreg_ppr_to_pnr() #1 { entry: unreachable }
define aarch64_sve_vector_pcs void @spills_fills_stack_id_zpr() #0 { entry: unreachable }
define aarch64_sve_vector_pcs void @spills_fills_stack_id_zpr2() #0 { entry: unreachable }
define aarch64_sve_vector_pcs void @spills_fills_stack_id_zpr2strided() #0 { entry: unreachable }
define aarch64_sve_vector_pcs void @spills_fills_stack_id_zpr3() #0 { entry: unreachable }
define aarch64_sve_vector_pcs void @spills_fills_stack_id_zpr4() #0 { entry: unreachable }
define aarch64_sve_vector_pcs void @spills_fills_stack_id_zpr4strided() #0 { entry: unreachable }
attributes #0 = { nounwind "target-features"="+sve" }
attributes #1 = { nounwind "target-features"="+sve2p1" }
...
---
name: spills_fills_stack_id_ppr
tracksRegLiveness: true
registers:
- { id: 0, class: ppr }
stack:
liveins:
- { reg: '$p0', virtual-reg: '%0' }
body: |
bb.0.entry:
liveins: $p0
; CHECK-LABEL: name: spills_fills_stack_id_ppr
; CHECK: stack:
; CHECK: - { id: 0, name: '', type: spill-slot, offset: 0, size: 2, alignment: 2
; CHECK-NEXT: stack-id: scalable-vector, callee-saved-register: ''
; EXPAND-LABEL: name: spills_fills_stack_id_ppr
; EXPAND: STR_PXI $p0, $sp, 7
; EXPAND: $p0 = LDR_PXI $sp, 7
%0:ppr = COPY $p0
$p0 = IMPLICIT_DEF
$p1 = IMPLICIT_DEF
$p2 = IMPLICIT_DEF
$p3 = IMPLICIT_DEF
$p4 = IMPLICIT_DEF
$p5 = IMPLICIT_DEF
$p6 = IMPLICIT_DEF
$p7 = IMPLICIT_DEF
$p8 = IMPLICIT_DEF
$p9 = IMPLICIT_DEF
$p10 = IMPLICIT_DEF
$p11 = IMPLICIT_DEF
$p12 = IMPLICIT_DEF
$p13 = IMPLICIT_DEF
$p14 = IMPLICIT_DEF
$p15 = IMPLICIT_DEF
$p0 = COPY %0
RET_ReallyLR
...
---
name: spills_fills_stack_id_ppr2
tracksRegLiveness: true
registers:
- { id: 0, class: ppr2 }
stack:
liveins:
- { reg: '$p0_p1', virtual-reg: '%0' }
body: |
bb.0.entry:
liveins: $p0_p1
; CHECK-LABEL: name: spills_fills_stack_id_ppr2
; CHECK: stack:
; CHECK: - { id: 0, name: '', type: spill-slot, offset: 0, size: 4, alignment: 2
; CHECK-NEXT: stack-id: scalable-vector, callee-saved-register: ''
; EXPAND-LABEL: name: spills_fills_stack_id_ppr2
; EXPAND: STR_PXI $p0, $sp, 6
; EXPAND: STR_PXI $p1, $sp, 7
; EXPAND: $p0 = LDR_PXI $sp, 6
; EXPAND: $p1 = LDR_PXI $sp, 7
%0:ppr2 = COPY $p0_p1
$p0 = IMPLICIT_DEF
$p1 = IMPLICIT_DEF
$p2 = IMPLICIT_DEF
$p3 = IMPLICIT_DEF
$p4 = IMPLICIT_DEF
$p5 = IMPLICIT_DEF
$p6 = IMPLICIT_DEF
$p7 = IMPLICIT_DEF
$p8 = IMPLICIT_DEF
$p9 = IMPLICIT_DEF
$p10 = IMPLICIT_DEF
$p11 = IMPLICIT_DEF
$p12 = IMPLICIT_DEF
$p13 = IMPLICIT_DEF
$p14 = IMPLICIT_DEF
$p15 = IMPLICIT_DEF
$p0_p1 = COPY %0
RET_ReallyLR
...
---
name: spills_fills_stack_id_ppr2mul2
tracksRegLiveness: true
registers:
- { id: 0, class: ppr2mul2 }
stack:
liveins:
- { reg: '$p0_p1', virtual-reg: '%0' }
body: |
bb.0.entry:
liveins: $p0_p1
; CHECK-LABEL: name: spills_fills_stack_id_ppr2
; CHECK: stack:
; CHECK: - { id: 0, name: '', type: spill-slot, offset: 0, size: 4, alignment: 2
; CHECK-NEXT: stack-id: scalable-vector, callee-saved-register: ''
; EXPAND-LABEL: name: spills_fills_stack_id_ppr2mul2
; EXPAND: STR_PXI $p0, $sp, 6
; EXPAND: STR_PXI $p1, $sp, 7
; EXPAND: $p0 = LDR_PXI $sp, 6
; EXPAND: $p1 = LDR_PXI $sp, 7
%0:ppr2mul2 = COPY $p0_p1
$p0 = IMPLICIT_DEF
$p1 = IMPLICIT_DEF
$p2 = IMPLICIT_DEF
$p3 = IMPLICIT_DEF
$p4 = IMPLICIT_DEF
$p5 = IMPLICIT_DEF
$p6 = IMPLICIT_DEF
$p7 = IMPLICIT_DEF
$p8 = IMPLICIT_DEF
$p9 = IMPLICIT_DEF
$p10 = IMPLICIT_DEF
$p11 = IMPLICIT_DEF
$p12 = IMPLICIT_DEF
$p13 = IMPLICIT_DEF
$p14 = IMPLICIT_DEF
$p15 = IMPLICIT_DEF
$p0_p1 = COPY %0
RET_ReallyLR
...
---
name: spills_fills_stack_id_pnr
tracksRegLiveness: true
registers:
- { id: 0, class: pnr }
stack:
liveins:
- { reg: '$pn0', virtual-reg: '%0' }
body: |
bb.0.entry:
liveins: $pn0
; CHECK-LABEL: name: spills_fills_stack_id_pnr
; CHECK: stack:
; CHECK: - { id: 0, name: '', type: spill-slot, offset: 0, size: 2, alignment: 2
; CHECK-NEXT: stack-id: scalable-vector, callee-saved-register: ''
; EXPAND-LABEL: name: spills_fills_stack_id_pnr
; EXPAND: STR_PXI $pn0, $sp, 7
; EXPAND: $pn0 = LDR_PXI $sp, 7, implicit-def $pn0
%0:pnr = COPY $pn0
$pn0 = IMPLICIT_DEF
$pn1 = IMPLICIT_DEF
$pn2 = IMPLICIT_DEF
$pn3 = IMPLICIT_DEF
$pn4 = IMPLICIT_DEF
$pn5 = IMPLICIT_DEF
$pn6 = IMPLICIT_DEF
$pn7 = IMPLICIT_DEF
$pn8 = IMPLICIT_DEF
$pn9 = IMPLICIT_DEF
$pn10 = IMPLICIT_DEF
$pn11 = IMPLICIT_DEF
$pn12 = IMPLICIT_DEF
$pn13 = IMPLICIT_DEF
$pn14 = IMPLICIT_DEF
$pn15 = IMPLICIT_DEF
$pn0 = COPY %0
RET_ReallyLR
...
---
name: spills_fills_stack_id_virtreg_pnr
tracksRegLiveness: true
registers:
- { id: 0, class: pnr_p8to15 }
stack:
body: |
bb.0.entry:
; CHECK-LABEL: name: spills_fills_stack_id_virtreg_pnr
; CHECK: stack:
; CHECK: - { id: 0, name: '', type: spill-slot, offset: 0, size: 2, alignment: 2
; CHECK-NEXT: stack-id: scalable-vector, callee-saved-register: ''
; EXPAND-LABEL: name: spills_fills_stack_id_virtreg_pnr
; EXPAND: renamable $pn8 = WHILEGE_CXX_B
; EXPAND: STR_PXI killed renamable $pn8, $sp, 7
;
; EXPAND: renamable $pn8 = LDR_PXI $sp, 7
; EXPAND-NEXT: $p0 = PEXT_PCI_B killed renamable $pn8, 0
%0:pnr_p8to15 = WHILEGE_CXX_B undef $x0, undef $x0, 0, implicit-def dead $nzcv
$pn0 = IMPLICIT_DEF
$pn1 = IMPLICIT_DEF
$pn2 = IMPLICIT_DEF
$pn3 = IMPLICIT_DEF
$pn4 = IMPLICIT_DEF
$pn5 = IMPLICIT_DEF
$pn6 = IMPLICIT_DEF
$pn7 = IMPLICIT_DEF
$pn8 = IMPLICIT_DEF
$pn9 = IMPLICIT_DEF
$pn10 = IMPLICIT_DEF
$pn11 = IMPLICIT_DEF
$pn12 = IMPLICIT_DEF
$pn13 = IMPLICIT_DEF
$pn14 = IMPLICIT_DEF
$pn15 = IMPLICIT_DEF
$p0 = PEXT_PCI_B %0, 0
RET_ReallyLR
...
---
name: spills_fills_stack_id_virtreg_ppr_to_pnr
tracksRegLiveness: true
registers:
- { id: 0, class: ppr }
- { id: 1, class: pnr_p8to15 }
stack:
body: |
bb.0.entry:
liveins: $p0
%0:ppr = COPY $p0
$pn0 = IMPLICIT_DEF
$pn1 = IMPLICIT_DEF
$pn2 = IMPLICIT_DEF
$pn3 = IMPLICIT_DEF
$pn4 = IMPLICIT_DEF
$pn5 = IMPLICIT_DEF
$pn6 = IMPLICIT_DEF
$pn7 = IMPLICIT_DEF
$pn8 = IMPLICIT_DEF
$pn9 = IMPLICIT_DEF
$pn10 = IMPLICIT_DEF
$pn11 = IMPLICIT_DEF
$pn12 = IMPLICIT_DEF
$pn13 = IMPLICIT_DEF
$pn14 = IMPLICIT_DEF
$pn15 = IMPLICIT_DEF
%1:pnr_p8to15 = COPY %0
$p0 = PEXT_PCI_B %1, 0
RET_ReallyLR
...
---
name: spills_fills_stack_id_zpr
tracksRegLiveness: true
registers:
- { id: 0, class: zpr }
stack:
liveins:
- { reg: '$z0', virtual-reg: '%0' }
body: |
bb.0.entry:
liveins: $z0
; CHECK-LABEL: name: spills_fills_stack_id_zpr
; CHECK: stack:
; CHECK: - { id: 0, name: '', type: spill-slot, offset: 0, size: 16, alignment: 16
; CHECK-NEXT: stack-id: scalable-vector, callee-saved-register: ''
; EXPAND-LABEL: name: spills_fills_stack_id_zpr
; EXPAND: STR_ZXI $z0, $sp, 0
; EXPAND: $z0 = LDR_ZXI $sp, 0
%0:zpr = COPY $z0
$z0_z1_z2_z3 = IMPLICIT_DEF
$z4_z5_z6_z7 = IMPLICIT_DEF
$z8_z9_z10_z11 = IMPLICIT_DEF
$z12_z13_z14_z15 = IMPLICIT_DEF
$z16_z17_z18_z19 = IMPLICIT_DEF
$z20_z21_z22_z23 = IMPLICIT_DEF
$z24_z25_z26_z27 = IMPLICIT_DEF
$z28_z29_z30_z31 = IMPLICIT_DEF
$z0 = COPY %0
RET_ReallyLR
...
---
name: spills_fills_stack_id_zpr2
tracksRegLiveness: true
registers:
- { id: 0, class: zpr2 }
stack:
liveins:
- { reg: '$z0_z1', virtual-reg: '%0' }
body: |
bb.0.entry:
liveins: $z0_z1
; CHECK-LABEL: name: spills_fills_stack_id_zpr2
; CHECK: stack:
; CHECK: - { id: 0, name: '', type: spill-slot, offset: 0, size: 32, alignment: 16
; CHECK-NEXT: stack-id: scalable-vector
; EXPAND-LABEL: name: spills_fills_stack_id_zpr2
; EXPAND: STR_ZXI $z0, $sp, 0
; EXPAND: STR_ZXI $z1, $sp, 1
; EXPAND: $z0 = LDR_ZXI $sp, 0
; EXPAND: $z1 = LDR_ZXI $sp, 1
%0:zpr2 = COPY $z0_z1
$z0_z1_z2_z3 = IMPLICIT_DEF
$z4_z5_z6_z7 = IMPLICIT_DEF
$z8_z9_z10_z11 = IMPLICIT_DEF
$z12_z13_z14_z15 = IMPLICIT_DEF
$z16_z17_z18_z19 = IMPLICIT_DEF
$z20_z21_z22_z23 = IMPLICIT_DEF
$z24_z25_z26_z27 = IMPLICIT_DEF
$z28_z29_z30_z31 = IMPLICIT_DEF
$z0_z1 = COPY %0
RET_ReallyLR
...
---
name: spills_fills_stack_id_zpr2strided
tracksRegLiveness: true
registers:
- { id: 0, class: zpr2strided }
stack:
liveins:
- { reg: '$z0_z8', virtual-reg: '%0' }
body: |
bb.0.entry:
liveins: $z0_z1
successors: %bb.1
$z0_z8 = COPY $z0_z1
B %bb.1
bb.1:
liveins: $z0_z8
; CHECK-LABEL: name: spills_fills_stack_id_zpr2strided
; CHECK: stack:
; CHECK: - { id: 0, name: '', type: spill-slot, offset: 0, size: 32, alignment: 16
; CHECK-NEXT: stack-id: scalable-vector
; EXPAND-LABEL: name: spills_fills_stack_id_zpr2strided
; EXPAND: STR_ZXI $z0, $sp, 0
; EXPAND: STR_ZXI $z8, $sp, 1
; EXPAND: $z0 = LDR_ZXI $sp, 0
; EXPAND: $z8 = LDR_ZXI $sp, 1
%0:zpr2strided = COPY $z0_z8
$z0_z1_z2_z3 = IMPLICIT_DEF
$z4_z5_z6_z7 = IMPLICIT_DEF
$z8_z9_z10_z11 = IMPLICIT_DEF
$z12_z13_z14_z15 = IMPLICIT_DEF
$z16_z17_z18_z19 = IMPLICIT_DEF
$z20_z21_z22_z23 = IMPLICIT_DEF
$z24_z25_z26_z27 = IMPLICIT_DEF
$z28_z29_z30_z31 = IMPLICIT_DEF
$z0_z8 = COPY %0
RET_ReallyLR
...
---
name: spills_fills_stack_id_zpr3
tracksRegLiveness: true
registers:
- { id: 0, class: zpr3 }
stack:
liveins:
- { reg: '$z0_z1_z2', virtual-reg: '%0' }
body: |
bb.0.entry:
liveins: $z0_z1_z2
; CHECK-LABEL: name: spills_fills_stack_id_zpr3
; CHECK: stack:
; CHECK: - { id: 0, name: '', type: spill-slot, offset: 0, size: 48, alignment: 16
; CHECK-NEXT: stack-id: scalable-vector
; EXPAND-LABEL: name: spills_fills_stack_id_zpr3
; EXPAND: STR_ZXI $z0, $sp, 0
; EXPAND: STR_ZXI $z1, $sp, 1
; EXPAND: STR_ZXI $z2, $sp, 2
; EXPAND: $z0 = LDR_ZXI $sp, 0
; EXPAND: $z1 = LDR_ZXI $sp, 1
; EXPAND: $z2 = LDR_ZXI $sp, 2
%0:zpr3 = COPY $z0_z1_z2
$z0_z1_z2_z3 = IMPLICIT_DEF
$z4_z5_z6_z7 = IMPLICIT_DEF
$z8_z9_z10_z11 = IMPLICIT_DEF
$z12_z13_z14_z15 = IMPLICIT_DEF
$z16_z17_z18_z19 = IMPLICIT_DEF
$z20_z21_z22_z23 = IMPLICIT_DEF
$z24_z25_z26_z27 = IMPLICIT_DEF
$z28_z29_z30_z31 = IMPLICIT_DEF
$z0_z1_z2 = COPY %0
RET_ReallyLR
...
---
name: spills_fills_stack_id_zpr4
tracksRegLiveness: true
registers:
- { id: 0, class: zpr4 }
stack:
liveins:
- { reg: '$z0_z1_z2_z3', virtual-reg: '%0' }
body: |
bb.0.entry:
liveins: $z0_z1_z2_z3
; CHECK-LABEL: name: spills_fills_stack_id_zpr4
; CHECK: stack:
; CHECK: - { id: 0, name: '', type: spill-slot, offset: 0, size: 64, alignment: 16
; CHECK-NEXT: stack-id: scalable-vector
; EXPAND-LABEL: name: spills_fills_stack_id_zpr4
; EXPAND: STR_ZXI $z0, $sp, 0
; EXPAND: STR_ZXI $z1, $sp, 1
; EXPAND: STR_ZXI $z2, $sp, 2
; EXPAND: STR_ZXI $z3, $sp, 3
; EXPAND: $z0 = LDR_ZXI $sp, 0
; EXPAND: $z1 = LDR_ZXI $sp, 1
; EXPAND: $z2 = LDR_ZXI $sp, 2
; EXPAND: $z3 = LDR_ZXI $sp, 3
%0:zpr4 = COPY $z0_z1_z2_z3
$z0_z1_z2_z3 = IMPLICIT_DEF
$z4_z5_z6_z7 = IMPLICIT_DEF
$z8_z9_z10_z11 = IMPLICIT_DEF
$z12_z13_z14_z15 = IMPLICIT_DEF
$z16_z17_z18_z19 = IMPLICIT_DEF
$z20_z21_z22_z23 = IMPLICIT_DEF
$z24_z25_z26_z27 = IMPLICIT_DEF
$z28_z29_z30_z31 = IMPLICIT_DEF
$z0_z1_z2_z3 = COPY %0
RET_ReallyLR
...
---
name: spills_fills_stack_id_zpr4strided
tracksRegLiveness: true
registers:
- { id: 0, class: zpr4strided }
stack:
liveins:
- { reg: '$z0_z4_z8_z12', virtual-reg: '%0' }
body: |
bb.0.entry:
liveins: $z0_z1_z2_z3
$z0_z4_z8_z12 = COPY $z0_z1_z2_z3
B %bb.1
bb.1:
liveins: $z0_z4_z8_z12
; CHECK-LABEL: name: spills_fills_stack_id_zpr4strided
; CHECK: stack:
; CHECK: - { id: 0, name: '', type: spill-slot, offset: 0, size: 64, alignment: 16
; CHECK-NEXT: stack-id: scalable-vector
; EXPAND-LABEL: name: spills_fills_stack_id_zpr4strided
; EXPAND: STR_ZXI $z0, $sp, 0
; EXPAND: STR_ZXI $z4, $sp, 1
; EXPAND: STR_ZXI $z8, $sp, 2
; EXPAND: STR_ZXI $z12, $sp, 3
; EXPAND: $z0 = LDR_ZXI $sp, 0
; EXPAND: $z4 = LDR_ZXI $sp, 1
; EXPAND: $z8 = LDR_ZXI $sp, 2
; EXPAND: $z12 = LDR_ZXI $sp, 3
%0:zpr4strided = COPY $z0_z4_z8_z12
$z0_z1_z2_z3 = IMPLICIT_DEF
$z4_z5_z6_z7 = IMPLICIT_DEF
$z8_z9_z10_z11 = IMPLICIT_DEF
$z12_z13_z14_z15 = IMPLICIT_DEF
$z16_z17_z18_z19 = IMPLICIT_DEF
$z20_z21_z22_z23 = IMPLICIT_DEF
$z24_z25_z26_z27 = IMPLICIT_DEF
$z28_z29_z30_z31 = IMPLICIT_DEF
$z0_z4_z8_z12 = COPY %0
RET_ReallyLR
...
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