# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve -run-pass=arm-low-overhead-loops --verify-machineinstrs %s -o - | FileCheck %s
#
--- |
@mask = external global i16
define dso_local void @test(ptr noalias nocapture %arg, ptr noalias nocapture readonly %arg1, i32 %arg2, ptr noalias nocapture readonly %arg3) local_unnamed_addr #0 {
bb:
%tmp = icmp eq i32 %arg2, 0
%tmp1 = add i32 %arg2, 3
%tmp2 = lshr i32 %tmp1, 2
%tmp3 = shl nuw i32 %tmp2, 2
%tmp4 = add i32 %tmp3, -4
%tmp5 = lshr i32 %tmp4, 2
%tmp6 = add nuw nsw i32 %tmp5, 1
%mask.gep9 = bitcast ptr @mask to ptr
%mask.load = load i16, ptr %mask.gep9
%conv.mask = zext i16 %mask.load to i32
%invariant.mask = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %conv.mask)
br i1 %tmp, label %bb27, label %bb3
bb3: ; preds = %bb
%start = call i32 @llvm.start.loop.iterations.i32(i32 %tmp6)
%scevgep1 = getelementptr i32, ptr %arg3, i32 -4
br label %bb9
bb9: ; preds = %bb9, %bb3
%lsr.iv4 = phi ptr [ %scevgep6, %bb9 ], [ %scevgep1, %bb3 ]
%lsr.iv2 = phi ptr [ %scevgep3, %bb9 ], [ %arg1, %bb3 ]
%lsr.iv = phi ptr [ %scevgep, %bb9 ], [ %arg, %bb3 ]
%tmp7 = phi i32 [ %start, %bb3 ], [ %tmp12, %bb9 ]
%tmp8 = phi i32 [ %arg2, %bb3 ], [ %tmp11, %bb9 ]
%lsr.iv1 = bitcast ptr %lsr.iv to ptr
%lsr.iv24 = bitcast ptr %lsr.iv2 to ptr
%lsr.iv47 = bitcast ptr %lsr.iv4 to ptr
%vctp = call <4 x i1> @llvm.arm.mve.vctp32(i32 %tmp8)
%and = and <4 x i1> %vctp, %invariant.mask
%tmp11 = sub i32 %tmp8, 4
%tmp17 = call <4 x i32> @llvm.masked.load.v4i32.p0(ptr %lsr.iv24, i32 4, <4 x i1> %and, <4 x i32> undef)
%tmp22 = call <4 x i32> @llvm.masked.load.v4i32.p0(ptr %lsr.iv1, i32 4, <4 x i1> %and, <4 x i32> undef)
%tmp23 = mul nsw <4 x i32> %tmp22, %tmp17
%scevgep2 = getelementptr <4 x i32>, ptr %lsr.iv47, i32 1
%load.limits = load <4 x i32>, ptr %scevgep2
%0 = insertelement <4 x i32> undef, i32 %conv.mask, i32 0
%1 = shufflevector <4 x i32> %0, <4 x i32> undef, <4 x i32> zeroinitializer
%bad.icmp = icmp ule <4 x i32> %load.limits, %1
call void @llvm.masked.store.v4i32.p0(<4 x i32> %tmp23, ptr %lsr.iv1, i32 4, <4 x i1> %bad.icmp)
%tmp12 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %tmp7, i32 1)
%tmp13 = icmp ne i32 %tmp12, 0
%scevgep = getelementptr i32, ptr %lsr.iv, i32 4
%scevgep3 = getelementptr i32, ptr %lsr.iv2, i32 4
%scevgep6 = getelementptr i32, ptr %lsr.iv4, i32 4
br i1 %tmp13, label %bb9, label %bb27
bb27: ; preds = %bb9, %bb
ret void
}
declare <4 x i32> @llvm.masked.load.v4i32.p0(ptr, i32 immarg, <4 x i1>, <4 x i32>)
declare void @llvm.masked.store.v4i32.p0(<4 x i32>, ptr, i32 immarg, <4 x i1>)
declare i32 @llvm.start.loop.iterations.i32(i32)
declare i32 @llvm.loop.decrement.reg.i32.i32.i32(i32, i32)
declare <4 x i1> @llvm.arm.mve.vctp32(i32)
declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32)
...
---
name: test
alignment: 2
exposesReturnsTwice: false
legalized: false
regBankSelected: false
selected: false
failedISel: false
tracksRegLiveness: true
hasWinCFI: false
registers: []
liveins:
- { reg: '$r0', virtual-reg: '' }
- { reg: '$r1', virtual-reg: '' }
- { reg: '$r2', virtual-reg: '' }
- { reg: '$r3', virtual-reg: '' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
hasStackMap: false
hasPatchPoint: false
stackSize: 20
offsetAdjustment: 0
maxAlignment: 4
adjustsStack: false
hasCalls: false
stackProtector: ''
maxCallFrameSize: 0
cvBytesOfCalleeSavedRegisters: 0
hasOpaqueSPAdjustment: false
hasVAStart: false
hasMustTailInVarArgFunc: false
localFrameSize: 0
savePoint: ''
restorePoint: ''
fixedStack: []
stack:
- { id: 0, name: '', type: spill-slot, offset: -20, size: 4, alignment: 4,
stack-id: default, callee-saved-register: '', callee-saved-restored: true,
debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
- { id: 1, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,
stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false,
debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
- { id: 2, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,
stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true,
debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
- { id: 3, name: '', type: spill-slot, offset: -12, size: 4, alignment: 4,
stack-id: default, callee-saved-register: '$r5', callee-saved-restored: true,
debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
- { id: 4, name: '', type: spill-slot, offset: -16, size: 4, alignment: 4,
stack-id: default, callee-saved-register: '$r4', callee-saved-restored: true,
debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
callSites: []
constants: []
machineFunctionInfo: {}
body: |
; CHECK-LABEL: name: test
; CHECK: bb.0.bb:
; CHECK-NEXT: successors: %bb.3(0x30000000), %bb.1(0x50000000)
; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r3, $r4, $r5, $r7
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $r5, killed $r7, killed $lr, implicit-def $sp, implicit $sp
; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 16
; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -4
; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r7, -8
; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r5, -12
; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r4, -16
; CHECK-NEXT: $sp = frame-setup tSUBspi $sp, 1, 14 /* CC::al */, $noreg
; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 20
; CHECK-NEXT: tCBZ $r2, %bb.3
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.1.bb3:
; CHECK-NEXT: successors: %bb.2(0x80000000)
; CHECK-NEXT: liveins: $r0, $r1, $r2, $r3
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: $r12 = t2MOVi16 target-flags(arm-lo16) @mask, 14 /* CC::al */, $noreg
; CHECK-NEXT: renamable $r4, dead $cpsr = tADDi3 renamable $r2, 3, 14 /* CC::al */, $noreg
; CHECK-NEXT: $r12 = t2MOVTi16 killed $r12, target-flags(arm-hi16) @mask, 14 /* CC::al */, $noreg
; CHECK-NEXT: renamable $r4 = t2BICri killed renamable $r4, 3, 14 /* CC::al */, $noreg, $noreg
; CHECK-NEXT: renamable $r5 = t2LDRHi12 killed renamable $r12, 0, 14 /* CC::al */, $noreg :: (dereferenceable load (s16) from %ir.mask.gep9)
; CHECK-NEXT: renamable $r12 = t2SUBri killed renamable $r4, 4, 14 /* CC::al */, $noreg, $noreg
; CHECK-NEXT: renamable $r4, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg
; CHECK-NEXT: $vpr = VMSR_P0 $r5, 14 /* CC::al */, $noreg
; CHECK-NEXT: renamable $lr = nuw nsw t2ADDrs killed renamable $r4, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg
; CHECK-NEXT: renamable $r12 = t2SUBri killed renamable $r3, 16, 14 /* CC::al */, $noreg, $noreg
; CHECK-NEXT: VSTR_P0_off killed renamable $vpr, $sp, 0, 14 /* CC::al */, $noreg :: (store (s32) into %stack.0)
; CHECK-NEXT: renamable $q0 = MVE_VDUP32 killed renamable $r5, 0, $noreg, $noreg, undef renamable $q0
; CHECK-NEXT: $r3 = tMOVr $r0, 14 /* CC::al */, $noreg
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2.bb9:
; CHECK-NEXT: successors: %bb.2(0x7c000000), %bb.3(0x04000000)
; CHECK-NEXT: liveins: $lr, $q0, $r0, $r1, $r2, $r3, $r12
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: renamable $vpr = VLDR_P0_off $sp, 0, 14 /* CC::al */, $noreg :: (load (s32) from %stack.0)
; CHECK-NEXT: MVE_VPST 2, implicit $vpr
; CHECK-NEXT: renamable $vpr = MVE_VCTP32 renamable $r2, 1, killed renamable $vpr, $noreg
; CHECK-NEXT: renamable $r1, renamable $q1 = MVE_VLDRWU32_post killed renamable $r1, 16, 1, renamable $vpr, $noreg :: (load (s128) from %ir.lsr.iv24, align 4)
; CHECK-NEXT: renamable $r3, renamable $q2 = MVE_VLDRWU32_post killed renamable $r3, 16, 1, killed renamable $vpr, $noreg :: (load (s128) from %ir.lsr.iv1, align 4)
; CHECK-NEXT: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg
; CHECK-NEXT: renamable $q1 = nsw MVE_VMULi32 killed renamable $q2, killed renamable $q1, 0, $noreg, $noreg, undef renamable $q1
; CHECK-NEXT: renamable $r12, renamable $q2 = MVE_VLDRWU32_pre killed renamable $r12, 16, 0, $noreg, $noreg :: (load (s128) from %ir.scevgep2, align 8)
; CHECK-NEXT: MVE_VPTv4u32 8, renamable $q0, killed renamable $q2, 2, implicit-def $vpr
; CHECK-NEXT: MVE_VSTRWU32 killed renamable $q1, killed renamable $r0, 0, 1, killed renamable $vpr, $noreg :: (store (s128) into %ir.lsr.iv1, align 4)
; CHECK-NEXT: $r0 = tMOVr $r3, 14 /* CC::al */, $noreg
; CHECK-NEXT: $lr = t2LEUpdate killed renamable $lr, %bb.2
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.3.bb27:
; CHECK-NEXT: $sp = tADDspi $sp, 1, 14 /* CC::al */, $noreg
; CHECK-NEXT: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $r5, def $r7, def $pc
bb.0.bb:
successors: %bb.3(0x30000000), %bb.1(0x50000000)
liveins: $r0, $r1, $r2, $r3, $r4, $r5, $r7, $lr
frame-setup tPUSH 14, $noreg, killed $r4, killed $r5, killed $r7, killed $lr, implicit-def $sp, implicit $sp
frame-setup CFI_INSTRUCTION def_cfa_offset 16
frame-setup CFI_INSTRUCTION offset $lr, -4
frame-setup CFI_INSTRUCTION offset $r7, -8
frame-setup CFI_INSTRUCTION offset $r5, -12
frame-setup CFI_INSTRUCTION offset $r4, -16
$sp = frame-setup tSUBspi $sp, 1, 14, $noreg
frame-setup CFI_INSTRUCTION def_cfa_offset 20
tCBZ $r2, %bb.3
bb.1.bb3:
successors: %bb.2(0x80000000)
liveins: $r0, $r1, $r2, $r3
$r12 = t2MOVi16 target-flags(arm-lo16) @mask, 14, $noreg
renamable $r4, dead $cpsr = tADDi3 renamable $r2, 3, 14, $noreg
$r12 = t2MOVTi16 killed $r12, target-flags(arm-hi16) @mask, 14, $noreg
renamable $r4 = t2BICri killed renamable $r4, 3, 14, $noreg, $noreg
renamable $r5 = t2LDRHi12 killed renamable $r12, 0, 14, $noreg :: (dereferenceable load (s16) from %ir.mask.gep9)
renamable $r12 = t2SUBri killed renamable $r4, 4, 14, $noreg, $noreg
renamable $r4, dead $cpsr = tMOVi8 1, 14, $noreg
$vpr = VMSR_P0 $r5, 14, $noreg
renamable $lr = nuw nsw t2ADDrs killed renamable $r4, killed renamable $r12, 19, 14, $noreg, $noreg
renamable $r12 = t2SUBri killed renamable $r3, 16, 14, $noreg, $noreg
VSTR_P0_off killed renamable $vpr, $sp, 0, 14, $noreg :: (store (s32) into %stack.0)
renamable $q0 = MVE_VDUP32 killed renamable $r5, 0, $noreg, $noreg, undef renamable $q0
$r3 = tMOVr $r0, 14, $noreg
$lr = t2DoLoopStart renamable $lr
bb.2.bb9:
successors: %bb.2(0x7c000000), %bb.3(0x04000000)
liveins: $lr, $q0, $r0, $r1, $r2, $r3, $r12
renamable $vpr = VLDR_P0_off $sp, 0, 14, $noreg :: (load (s32) from %stack.0)
MVE_VPST 2, implicit $vpr
renamable $vpr = MVE_VCTP32 renamable $r2, 1, killed renamable $vpr, $noreg
renamable $r1, renamable $q1 = MVE_VLDRWU32_post killed renamable $r1, 16, 1, renamable $vpr, $noreg :: (load (s128) from %ir.lsr.iv24, align 4)
renamable $r3, renamable $q2 = MVE_VLDRWU32_post killed renamable $r3, 16, 1, killed renamable $vpr, $noreg :: (load (s128) from %ir.lsr.iv1, align 4)
renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14, $noreg
renamable $q1 = nsw MVE_VMULi32 killed renamable $q2, killed renamable $q1, 0, $noreg, $noreg, undef renamable $q1
renamable $r12, renamable $q2 = MVE_VLDRWU32_pre killed renamable $r12, 16, 0, $noreg, $noreg :: (load (s128) from %ir.scevgep2, align 8)
MVE_VPTv4u32 8, renamable $q0, killed renamable $q2, 2, implicit-def $vpr
MVE_VSTRWU32 killed renamable $q1, killed renamable $r0, 0, 1, killed renamable $vpr, $noreg :: (store (s128) into %ir.lsr.iv1, align 4)
renamable $lr = t2LoopDec killed renamable $lr, 1
$r0 = tMOVr $r3, 14, $noreg
t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr
tB %bb.3, 14, $noreg
bb.3.bb27:
$sp = tADDspi $sp, 1, 14, $noreg
tPOP_RET 14, $noreg, def $r4, def $r5, def $r7, def $pc
...
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