# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve -run-pass=arm-low-overhead-loops %s -o - | FileCheck %s
--- |
define hidden void @vector_spill_in_loop() {
entry:
ret void
}
define hidden void @vector_spill_load_outside() {
entry:
ret void
}
...
---
name: vector_spill_in_loop
tracksRegLiveness: true
stack:
- { id: 0, name: '', type: spill-slot, offset: -120, size: 16, alignment: 8,
stack-id: default, callee-saved-register: '', callee-saved-restored: true,
debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
body: |
; CHECK-LABEL: name: vector_spill_in_loop
; CHECK: bb.0:
; CHECK-NEXT: successors: %bb.1(0x80000000)
; CHECK-NEXT: liveins: $q0, $r1, $r2, $r3, $r4, $r5, $r7, $r8, $r10, $r11, $r12
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: $r6 = tMOVr $r2, 14 /* CC::al */, $noreg
; CHECK-NEXT: $r0 = tMOVr $r12, 14 /* CC::al */, $noreg
; CHECK-NEXT: $lr = MVE_DLSTP_16 renamable $r3
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.1:
; CHECK-NEXT: successors: %bb.1(0x7c000000), %bb.2(0x04000000)
; CHECK-NEXT: liveins: $lr, $q0, $r0, $r1, $r2, $r3, $r4, $r5, $r6, $r7, $r8, $r10, $r11, $r12
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: renamable $r0, renamable $q6 = MVE_VLDRHU16_post killed renamable $r0, 16, 0, $noreg, $noreg
; CHECK-NEXT: renamable $q3 = MVE_VLDRHU16 renamable $r6, 0, 0, $noreg, $noreg
; CHECK-NEXT: renamable $q5 = MVE_VSHR_immu16 killed renamable $q3, 11, 0, $noreg, $noreg, undef renamable $q5
; CHECK-NEXT: MVE_VSTRWU32 killed renamable $q5, $sp, 80, 0, $noreg, $noreg :: (store (s128) into %stack.0, align 8)
; CHECK-NEXT: dead renamable $q7 = MVE_VLDRWU32 $sp, 80, 0, $noreg, $noreg :: (load (s128) from %stack.0, align 8)
; CHECK-NEXT: dead renamable $vpr = MVE_VCMPi16r killed renamable $q6, renamable $r8, 1, 0, killed $noreg, $noreg
; CHECK-NEXT: $lr = MVE_LETP killed renamable $lr, %bb.1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2:
; CHECK-NEXT: successors: %bb.3(0x04000000), %bb.0(0x7c000000)
; CHECK-NEXT: liveins: $q0, $r1, $r2, $r3, $r4, $r5, $r7, $r8, $r10, $r11, $r12
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: renamable $r0 = tLDRspi $sp, 1, 14 /* CC::al */, $noreg
; CHECK-NEXT: renamable $r10 = nuw t2ADDri killed renamable $r10, 1, 14 /* CC::al */, $noreg, $noreg
; CHECK-NEXT: renamable $r12 = t2ADDrs killed renamable $r12, killed renamable $r0, 10, 14 /* CC::al */, $noreg, $noreg
; CHECK-NEXT: renamable $r0 = tLDRspi $sp, 3, 14 /* CC::al */, $noreg
; CHECK-NEXT: renamable $r2 = t2ADDrs killed renamable $r2, killed renamable $r0, 10, 14 /* CC::al */, $noreg, $noreg
; CHECK-NEXT: renamable $r0 = tLDRspi $sp, 2, 14 /* CC::al */, $noreg
; CHECK-NEXT: tCMPhir renamable $r10, killed renamable $r0, 14 /* CC::al */, $noreg, implicit-def $cpsr
; CHECK-NEXT: tBcc %bb.0, 1 /* CC::ne */, killed $cpsr
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.3:
; CHECK-NEXT: $sp = frame-destroy tADDspi $sp, 24, 14 /* CC::al */, $noreg
; CHECK-NEXT: $sp = frame-destroy VLDMDIA_UPD $sp, 14 /* CC::al */, $noreg, def $d8, def $d9, def $d10, def $d11, def $d12, def $d13, def $d14, def $d15
; CHECK-NEXT: $sp = frame-destroy tADDspi $sp, 1, 14 /* CC::al */, $noreg
; CHECK-NEXT: $sp = frame-destroy t2LDMIA_RET $sp, 14 /* CC::al */, $noreg, def $r4, def $r5, def $r6, def $r7, def $r8, def $r9, def $r10, def $r11, def $pc
bb.0:
successors: %bb.1(0x80000000)
liveins: $q0, $r1, $r2, $r3, $r4, $r5, $r7, $r8, $r10, $r11, $r12
$r6 = tMOVr $r2, 14 /* CC::al */, $noreg
$r0 = tMOVr $r12, 14 /* CC::al */, $noreg
$r9 = tMOVr $r3, 14 /* CC::al */, $noreg
renamable $lr = t2DoLoopStartTP renamable $r1, renamable $r3
bb.1:
successors: %bb.1(0x7c000000), %bb.2(0x04000000)
liveins: $lr, $q0, $r0, $r1, $r2, $r3, $r4, $r5, $r6, $r7, $r8, $r9, $r10, $r11, $r12
renamable $vpr = MVE_VCTP16 renamable $r9, 0, $noreg, $noreg
MVE_VPST 8, implicit $vpr
renamable $r0, renamable $q6 = MVE_VLDRHU16_post killed renamable $r0, 16, 1, renamable $vpr, $noreg
renamable $q3 = MVE_VLDRHU16 renamable $r6, 0, 1, renamable $vpr, $noreg
MVE_VPST 2, implicit $vpr
renamable $q5 = MVE_VSHR_immu16 renamable $q3, 11, 1, renamable $vpr, $noreg, undef renamable $q5
renamable $r9 = nsw t2SUBri killed renamable $r9, 8, 14 /* CC::al */, $noreg, $noreg
MVE_VSTRWU32 killed renamable $q5, $sp, 80, 0, $noreg, $noreg :: (store (s128) into %stack.0, align 8)
MVE_VPST 8, implicit $vpr
renamable $q7 = MVE_VLDRWU32 $sp, 80, 0, $noreg, $noreg :: (load (s128) from %stack.0, align 8)
MVE_VPST 1, implicit $vpr
renamable $vpr = MVE_VCMPi16r killed renamable $q6, renamable $r8, 1, 1, killed renamable $vpr, $noreg
renamable $lr = t2LoopEndDec killed renamable $lr, %bb.1, implicit-def dead $cpsr
tB %bb.2, 14 /* CC::al */, $noreg
bb.2:
successors: %bb.3(0x04000000), %bb.0(0x7c000000)
liveins: $q0, $r1, $r2, $r3, $r4, $r5, $r7, $r8, $r10, $r11, $r12
renamable $r0 = tLDRspi $sp, 1, 14 /* CC::al */, $noreg
renamable $r10 = nuw t2ADDri killed renamable $r10, 1, 14 /* CC::al */, $noreg, $noreg
renamable $r12 = t2ADDrs killed renamable $r12, killed renamable $r0, 10, 14 /* CC::al */, $noreg, $noreg
renamable $r0 = tLDRspi $sp, 3, 14 /* CC::al */, $noreg
renamable $r2 = t2ADDrs killed renamable $r2, killed renamable $r0, 10, 14 /* CC::al */, $noreg, $noreg
renamable $r0 = tLDRspi $sp, 2, 14 /* CC::al */, $noreg
tCMPhir renamable $r10, killed renamable $r0, 14 /* CC::al */, $noreg, implicit-def $cpsr
tBcc %bb.0, 1 /* CC::ne */, killed $cpsr
bb.3:
$sp = frame-destroy tADDspi $sp, 24, 14 /* CC::al */, $noreg
$sp = frame-destroy VLDMDIA_UPD $sp, 14 /* CC::al */, $noreg, def $d8, def $d9, def $d10, def $d11, def $d12, def $d13, def $d14, def $d15
$sp = frame-destroy tADDspi $sp, 1, 14 /* CC::al */, $noreg
$sp = frame-destroy t2LDMIA_RET $sp, 14 /* CC::al */, $noreg, def $r4, def $r5, def $r6, def $r7, def $r8, def $r9, def $r10, def $r11, def $pc
...
---
name: vector_spill_load_outside
stack:
- { id: 0, name: '', type: spill-slot, offset: -120, size: 16, alignment: 8,
stack-id: default, callee-saved-register: '', callee-saved-restored: true,
debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
tracksRegLiveness: true
body: |
; CHECK-LABEL: name: vector_spill_load_outside
; CHECK: bb.0:
; CHECK-NEXT: successors: %bb.1(0x80000000)
; CHECK-NEXT: liveins: $q0, $r1, $r2, $r3, $r4, $r5, $r7, $r8, $r10, $r11, $r12
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: $r6 = tMOVr $r2, 14 /* CC::al */, $noreg
; CHECK-NEXT: $r0 = tMOVr $r12, 14 /* CC::al */, $noreg
; CHECK-NEXT: $r9 = tMOVr $r3, 14 /* CC::al */, $noreg
; CHECK-NEXT: $lr = t2DLS renamable $r1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.1:
; CHECK-NEXT: successors: %bb.1(0x7c000000), %bb.2(0x04000000)
; CHECK-NEXT: liveins: $lr, $q0, $r0, $r1, $r2, $r3, $r4, $r5, $r6, $r7, $r8, $r9, $r10, $r11, $r12
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: renamable $vpr = MVE_VCTP16 renamable $r9, 0, $noreg, $noreg
; CHECK-NEXT: MVE_VPST 8, implicit $vpr
; CHECK-NEXT: renamable $r0, renamable $q6 = MVE_VLDRHU16_post killed renamable $r0, 16, 1, renamable $vpr, $noreg
; CHECK-NEXT: renamable $q3 = MVE_VLDRHU16 renamable $r6, 0, 1, renamable $vpr, $noreg
; CHECK-NEXT: MVE_VPST 2, implicit $vpr
; CHECK-NEXT: renamable $q5 = MVE_VSHR_immu16 killed renamable $q3, 11, 1, renamable $vpr, $noreg, undef renamable $q5
; CHECK-NEXT: renamable $r9 = nsw t2SUBri killed renamable $r9, 8, 14 /* CC::al */, $noreg, $noreg
; CHECK-NEXT: MVE_VSTRWU32 killed renamable $q5, $sp, 80, 0, $noreg, $noreg :: (store (s128) into %stack.0, align 8)
; CHECK-NEXT: MVE_VPST 8, implicit $vpr
; CHECK-NEXT: dead renamable $q7 = MVE_VLDRWU32 $sp, 80, 0, $noreg, $noreg :: (load (s128) from %stack.0, align 8)
; CHECK-NEXT: MVE_VPST 1, implicit $vpr
; CHECK-NEXT: dead renamable $vpr = MVE_VCMPi16r killed renamable $q6, renamable $r8, 1, 1, killed renamable $vpr, $noreg
; CHECK-NEXT: $lr = t2LEUpdate killed renamable $lr, %bb.1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2:
; CHECK-NEXT: successors: %bb.3(0x04000000), %bb.0(0x7c000000)
; CHECK-NEXT: liveins: $q0, $r1, $r2, $r3, $r4, $r5, $r7, $r8, $r10, $r11, $r12
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: dead renamable $q7 = MVE_VLDRWU32 $sp, 80, 0, $noreg, $noreg :: (load (s128) from %stack.0, align 8)
; CHECK-NEXT: renamable $r0 = tLDRspi $sp, 1, 14 /* CC::al */, $noreg
; CHECK-NEXT: renamable $r10 = nuw t2ADDri killed renamable $r10, 1, 14 /* CC::al */, $noreg, $noreg
; CHECK-NEXT: renamable $r12 = t2ADDrs killed renamable $r12, killed renamable $r0, 10, 14 /* CC::al */, $noreg, $noreg
; CHECK-NEXT: renamable $r0 = tLDRspi $sp, 3, 14 /* CC::al */, $noreg
; CHECK-NEXT: renamable $r2 = t2ADDrs killed renamable $r2, killed renamable $r0, 10, 14 /* CC::al */, $noreg, $noreg
; CHECK-NEXT: renamable $r0 = tLDRspi $sp, 2, 14 /* CC::al */, $noreg
; CHECK-NEXT: tCMPhir renamable $r10, killed renamable $r0, 14 /* CC::al */, $noreg, implicit-def $cpsr
; CHECK-NEXT: tBcc %bb.0, 1 /* CC::ne */, killed $cpsr
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.3:
; CHECK-NEXT: $sp = frame-destroy tADDspi $sp, 24, 14 /* CC::al */, $noreg
; CHECK-NEXT: $sp = frame-destroy VLDMDIA_UPD $sp, 14 /* CC::al */, $noreg, def $d8, def $d9, def $d10, def $d11, def $d12, def $d13, def $d14, def $d15
; CHECK-NEXT: $sp = frame-destroy tADDspi $sp, 1, 14 /* CC::al */, $noreg
; CHECK-NEXT: $sp = frame-destroy t2LDMIA_RET $sp, 14 /* CC::al */, $noreg, def $r4, def $r5, def $r6, def $r7, def $r8, def $r9, def $r10, def $r11, def $pc
bb.0:
successors: %bb.1(0x80000000)
liveins: $q0, $r1, $r2, $r3, $r4, $r5, $r7, $r8, $r10, $r11, $r12
$r6 = tMOVr $r2, 14 /* CC::al */, $noreg
$r0 = tMOVr $r12, 14 /* CC::al */, $noreg
$r9 = tMOVr $r3, 14 /* CC::al */, $noreg
renamable $lr = t2DoLoopStartTP renamable $r1, renamable $r3
bb.1:
successors: %bb.1(0x7c000000), %bb.2(0x04000000)
liveins: $lr, $q0, $r0, $r1, $r2, $r3, $r4, $r5, $r6, $r7, $r8, $r9, $r10, $r11, $r12
renamable $vpr = MVE_VCTP16 renamable $r9, 0, $noreg, $noreg
MVE_VPST 8, implicit $vpr
renamable $r0, renamable $q6 = MVE_VLDRHU16_post killed renamable $r0, 16, 1, renamable $vpr, $noreg
renamable $q3 = MVE_VLDRHU16 renamable $r6, 0, 1, renamable $vpr, $noreg
MVE_VPST 2, implicit $vpr
renamable $q5 = MVE_VSHR_immu16 renamable $q3, 11, 1, renamable $vpr, $noreg, undef renamable $q5
renamable $r9 = nsw t2SUBri killed renamable $r9, 8, 14 /* CC::al */, $noreg, $noreg
MVE_VSTRWU32 killed renamable $q5, $sp, 80, 0, $noreg, $noreg :: (store (s128) into %stack.0, align 8)
MVE_VPST 8, implicit $vpr
renamable $q7 = MVE_VLDRWU32 $sp, 80, 0, $noreg, $noreg :: (load (s128) from %stack.0, align 8)
MVE_VPST 1, implicit $vpr
renamable $vpr = MVE_VCMPi16r killed renamable $q6, renamable $r8, 1, 1, killed renamable $vpr, $noreg
renamable $lr = t2LoopEndDec killed renamable $lr, %bb.1, implicit-def dead $cpsr
tB %bb.2, 14 /* CC::al */, $noreg
bb.2:
successors: %bb.3(0x04000000), %bb.0(0x7c000000)
liveins: $q0, $r1, $r2, $r3, $r4, $r5, $r7, $r8, $r10, $r11, $r12
renamable $q7 = MVE_VLDRWU32 $sp, 80, 0, $noreg, $noreg :: (load (s128) from %stack.0, align 8)
renamable $r0 = tLDRspi $sp, 1, 14 /* CC::al */, $noreg
renamable $r10 = nuw t2ADDri killed renamable $r10, 1, 14 /* CC::al */, $noreg, $noreg
renamable $r12 = t2ADDrs killed renamable $r12, killed renamable $r0, 10, 14 /* CC::al */, $noreg, $noreg
renamable $r0 = tLDRspi $sp, 3, 14 /* CC::al */, $noreg
renamable $r2 = t2ADDrs killed renamable $r2, killed renamable $r0, 10, 14 /* CC::al */, $noreg, $noreg
renamable $r0 = tLDRspi $sp, 2, 14 /* CC::al */, $noreg
tCMPhir renamable $r10, killed renamable $r0, 14 /* CC::al */, $noreg, implicit-def $cpsr
tBcc %bb.0, 1 /* CC::ne */, killed $cpsr
bb.3:
$sp = frame-destroy tADDspi $sp, 24, 14 /* CC::al */, $noreg
$sp = frame-destroy VLDMDIA_UPD $sp, 14 /* CC::al */, $noreg, def $d8, def $d9, def $d10, def $d11, def $d12, def $d13, def $d14, def $d15
$sp = frame-destroy tADDspi $sp, 1, 14 /* CC::al */, $noreg
$sp = frame-destroy t2LDMIA_RET $sp, 14 /* CC::al */, $noreg, def $r4, def $r5, def $r6, def $r7, def $r8, def $r9, def $r10, def $r11, def $pc
...
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