# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve -run-pass=arm-low-overhead-loops %s -o - --verify-machineinstrs | FileCheck %s
# TODO: We should be able to handle the VCMP -> VPST -> VCMP -> VCTP case.
--- |
define dso_local arm_aapcs_vfpcc void @test(ptr noalias nocapture %a, ptr nocapture readonly %b, i32 %N) local_unnamed_addr #0 {
entry:
%cmp9 = icmp eq i32 %N, 0
%tmp = add i32 %N, 3
%tmp1 = lshr i32 %tmp, 2
%tmp2 = shl nuw i32 %tmp1, 2
%tmp3 = add i32 %tmp2, -4
%tmp4 = lshr i32 %tmp3, 2
%tmp5 = add nuw nsw i32 %tmp4, 1
br i1 %cmp9, label %for.cond.cleanup, label %vector.ph
vector.ph: ; preds = %entry
%div = lshr i32 %N, 1
%trip.count.minus.1 = add i32 %N, -1
%broadcast.splatinsert = insertelement <4 x i32> undef, i32 %trip.count.minus.1, i32 0
%broadcast.splat = shufflevector <4 x i32> %broadcast.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer
%start = call i32 @llvm.start.loop.iterations.i32(i32 %tmp5)
br label %vector.body
vector.body: ; preds = %vector.body, %vector.ph
%lsr.iv = phi i32 [ %lsr.iv.next, %vector.body ], [ %start, %vector.ph ]
%lsr.iv3 = phi ptr [ %scevgep4, %vector.body ], [ %b, %vector.ph ]
%lsr.iv1 = phi ptr [ %scevgep, %vector.body ], [ %a, %vector.ph ]
%vec.ind = phi <4 x i32> [ <i32 0, i32 1, i32 2, i32 3>, %vector.ph ], [ %vec.ind.next, %vector.body ]
%elts.rem = phi i32 [ %N, %vector.ph ], [ %elts.rem.next, %vector.body ]
%lsr.iv12 = bitcast ptr %lsr.iv1 to ptr
%lsr.iv35 = bitcast ptr %lsr.iv3 to ptr
%tmp7 = insertelement <4 x i32> undef, i32 %div, i32 0
%tmp8 = shufflevector <4 x i32> %tmp7, <4 x i32> undef, <4 x i32> zeroinitializer
%tmp9 = icmp ult <4 x i32> %vec.ind, %tmp8
%lower = icmp uge <4 x i32> %vec.ind, <i32 1, i32 1, i32 1, i32 1>
%tmp10 = call <4 x i1> @llvm.arm.mve.vctp32(i32 %elts.rem)
%tmp11 = and <4 x i1> %tmp9, %tmp10
%pred = and <4 x i1> %tmp11, %lower
%wide.masked.load = call <4 x i32> @llvm.masked.load.v4i32.p0(ptr %lsr.iv35, i32 4, <4 x i1> %pred, <4 x i32> undef)
call void @llvm.masked.store.v4i32.p0(<4 x i32> %wide.masked.load, ptr %lsr.iv12, i32 4, <4 x i1> %pred)
%vec.ind.next = add <4 x i32> %vec.ind, <i32 4, i32 4, i32 4, i32 4>
%elts.rem.next = sub i32 %elts.rem, 4
%scevgep = getelementptr i32, ptr %lsr.iv1, i32 4
%scevgep4 = getelementptr i32, ptr %lsr.iv3, i32 4
%tmp12 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %lsr.iv, i32 1)
%tmp13 = icmp ne i32 %tmp12, 0
%lsr.iv.next = add nsw i32 %lsr.iv, -1
br i1 %tmp13, label %vector.body, label %for.cond.cleanup
for.cond.cleanup: ; preds = %vector.body, %entry
ret void
}
declare <4 x i32> @llvm.masked.load.v4i32.p0(ptr, i32 immarg, <4 x i1>, <4 x i32>)
declare void @llvm.masked.store.v4i32.p0(<4 x i32>, ptr, i32 immarg, <4 x i1>)
declare <4 x i1> @llvm.arm.mve.vctp32(i32)
declare i32 @llvm.start.loop.iterations.i32(i32)
declare i32 @llvm.loop.decrement.reg.i32.i32.i32(i32, i32)
...
---
name: test
alignment: 16
tracksRegLiveness: true
registers: []
liveins:
- { reg: '$r0', virtual-reg: '' }
- { reg: '$r1', virtual-reg: '' }
- { reg: '$r2', virtual-reg: '' }
frameInfo:
stackSize: 24
offsetAdjustment: 0
maxAlignment: 8
fixedStack: []
stack:
- { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,
stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false,
debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
- { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,
stack-id: default, callee-saved-register: '$r4', callee-saved-restored: true,
debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
- { id: 2, name: '', type: spill-slot, offset: -16, size: 8, alignment: 8,
stack-id: default, callee-saved-register: '$d9', callee-saved-restored: true,
debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
- { id: 3, name: '', type: spill-slot, offset: -24, size: 8, alignment: 8,
stack-id: default, callee-saved-register: '$d8', callee-saved-restored: true,
debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
callSites: []
constants:
- id: 0
value: '<4 x i32> <i32 0, i32 1, i32 2, i32 3>'
alignment: 16
isTargetSpecific: false
machineFunctionInfo: {}
body: |
; CHECK-LABEL: name: test
; CHECK: bb.0.entry:
; CHECK-NEXT: successors: %bb.3(0x30000000), %bb.1(0x50000000)
; CHECK-NEXT: liveins: $lr, $d8, $d9, $r0, $r1, $r2, $r4
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp
; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 8
; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -4
; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r4, -8
; CHECK-NEXT: $sp = frame-setup VSTMDDB_UPD $sp, 14 /* CC::al */, $noreg, killed $d8, killed $d9
; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 24
; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $d9, -16
; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $d8, -24
; CHECK-NEXT: tCBZ $r2, %bb.3
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.1.vector.ph:
; CHECK-NEXT: successors: %bb.2(0x80000000)
; CHECK-NEXT: liveins: $r0, $r1, $r2
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: renamable $r3, dead $cpsr = tADDi3 renamable $r2, 3, 14 /* CC::al */, $noreg
; CHECK-NEXT: renamable $q2 = MVE_VMOVimmi32 1, 0, $noreg, $noreg, undef renamable $q2
; CHECK-NEXT: renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg
; CHECK-NEXT: renamable $q3 = MVE_VMOVimmi32 4, 0, $noreg, $noreg, undef renamable $q3
; CHECK-NEXT: renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg
; CHECK-NEXT: renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg
; CHECK-NEXT: renamable $r3 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg
; CHECK-NEXT: dead $lr = t2DLS renamable $r3
; CHECK-NEXT: $r4 = tMOVr killed $r3, 14 /* CC::al */, $noreg
; CHECK-NEXT: renamable $r3 = tLEApcrel %const.0, 14 /* CC::al */, $noreg
; CHECK-NEXT: renamable $q0 = MVE_VLDRWU32 killed renamable $r3, 0, 0, $noreg, $noreg :: (load (s128) from constant-pool)
; CHECK-NEXT: renamable $r3, dead $cpsr = tLSRri renamable $r2, 1, 14 /* CC::al */, $noreg
; CHECK-NEXT: renamable $q1 = MVE_VDUP32 killed renamable $r3, 0, $noreg, $noreg, undef renamable $q1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2.vector.body:
; CHECK-NEXT: successors: %bb.2(0x7c000000), %bb.3(0x04000000)
; CHECK-NEXT: liveins: $q0, $q1, $q2, $q3, $r0, $r1, $r2, $r4
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: $lr = tMOVr $r4, 14 /* CC::al */, $noreg
; CHECK-NEXT: renamable $r4, dead $cpsr = nsw tSUBi8 killed $r4, 1, 14 /* CC::al */, $noreg
; CHECK-NEXT: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg
; CHECK-NEXT: renamable $vpr = MVE_VCMPu32 renamable $q1, renamable $q0, 8, 0, $noreg, $noreg
; CHECK-NEXT: MVE_VPST 1, implicit $vpr
; CHECK-NEXT: renamable $vpr = MVE_VCMPu32 renamable $q0, renamable $q2, 2, 1, killed renamable $vpr, $noreg
; CHECK-NEXT: renamable $vpr = MVE_VCTP32 renamable $r2, 1, killed renamable $vpr, $noreg
; CHECK-NEXT: renamable $r1, renamable $q4 = MVE_VLDRWU32_post killed renamable $r1, 16, 1, renamable $vpr, $noreg :: (load (s128) from %ir.lsr.iv35, align 4)
; CHECK-NEXT: renamable $r0 = MVE_VSTRWU32_post killed renamable $q4, killed renamable $r0, 16, 1, killed renamable $vpr, $noreg :: (store (s128) into %ir.lsr.iv12, align 4)
; CHECK-NEXT: renamable $q0 = MVE_VADDi32 killed renamable $q0, renamable $q3, 0, $noreg, $noreg, undef renamable $q0
; CHECK-NEXT: dead $lr = t2LEUpdate killed renamable $lr, %bb.2
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.3.for.cond.cleanup:
; CHECK-NEXT: $sp = frame-destroy VLDMDIA_UPD $sp, 14 /* CC::al */, $noreg, def $d8, def $d9
; CHECK-NEXT: frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.4 (align 16):
; CHECK-NEXT: CONSTPOOL_ENTRY 0, %const.0, 16
bb.0.entry:
successors: %bb.3(0x30000000), %bb.1(0x50000000)
liveins: $r0, $r1, $r2, $r4, $lr, $d8, $d9
frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp
frame-setup CFI_INSTRUCTION def_cfa_offset 8
frame-setup CFI_INSTRUCTION offset $lr, -4
frame-setup CFI_INSTRUCTION offset $r4, -8
$sp = frame-setup VSTMDDB_UPD $sp, 14 /* CC::al */, $noreg, killed $d8, killed $d9
frame-setup CFI_INSTRUCTION def_cfa_offset 24
frame-setup CFI_INSTRUCTION offset $d9, -16
frame-setup CFI_INSTRUCTION offset $d8, -24
tCBZ $r2, %bb.3
bb.1.vector.ph:
successors: %bb.2(0x80000000)
liveins: $r0, $r1, $r2
renamable $r3, dead $cpsr = tADDi3 renamable $r2, 3, 14 /* CC::al */, $noreg
renamable $q2 = MVE_VMOVimmi32 1, 0, $noreg, $noreg, undef renamable $q2
renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg
renamable $q3 = MVE_VMOVimmi32 4, 0, $noreg, $noreg, undef renamable $q3
renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg
renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg
renamable $r3 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg
$lr = t2DoLoopStart renamable $r3
$r4 = tMOVr killed $r3, 14 /* CC::al */, $noreg
renamable $r3 = tLEApcrel %const.0, 14 /* CC::al */, $noreg
renamable $q0 = MVE_VLDRWU32 killed renamable $r3, 0, 0, $noreg, $noreg :: (load (s128) from constant-pool)
renamable $r3, dead $cpsr = tLSRri renamable $r2, 1, 14 /* CC::al */, $noreg
renamable $q1 = MVE_VDUP32 killed renamable $r3, 0, $noreg, $noreg, undef renamable $q1
bb.2.vector.body:
successors: %bb.2(0x7c000000), %bb.3(0x04000000)
liveins: $q0, $q1, $q2, $q3, $r0, $r1, $r2, $r4
$lr = tMOVr $r4, 14 /* CC::al */, $noreg
renamable $r4, dead $cpsr = nsw tSUBi8 killed $r4, 1, 14 /* CC::al */, $noreg
renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg
renamable $vpr = MVE_VCMPu32 renamable $q1, renamable $q0, 8, 0, $noreg, $noreg
MVE_VPST 1, implicit $vpr
renamable $vpr = MVE_VCMPu32 renamable $q0, renamable $q2, 2, 1, killed renamable $vpr, $noreg
renamable $vpr = MVE_VCTP32 renamable $r2, 1, killed renamable $vpr, $noreg
renamable $r1, renamable $q4 = MVE_VLDRWU32_post killed renamable $r1, 16, 1, renamable $vpr, $noreg :: (load (s128) from %ir.lsr.iv35, align 4)
renamable $r0 = MVE_VSTRWU32_post killed renamable $q4, killed renamable $r0, 16, 1, killed renamable $vpr, $noreg :: (store (s128) into %ir.lsr.iv12, align 4)
renamable $q0 = MVE_VADDi32 killed renamable $q0, renamable $q3, 0, $noreg, $noreg, undef renamable $q0
renamable $lr = t2LoopDec killed renamable $lr, 1
t2LoopEnd killed renamable $lr, %bb.2, implicit-def dead $cpsr
tB %bb.3, 14 /* CC::al */, $noreg
bb.3.for.cond.cleanup:
$sp = frame-destroy VLDMDIA_UPD $sp, 14 /* CC::al */, $noreg, def $d8, def $d9
frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc
bb.4 (align 16):
CONSTPOOL_ENTRY 0, %const.0, 16
...
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