# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve.fp -run-pass=arm-low-overhead-loops --verify-machineinstrs %s -o - | FileCheck %s
--- |
define dso_local arm_aapcs_vfpcc void @remove_mov_lr_chain(ptr nocapture readonly %pSrc, ptr nocapture %pDst, i32 %blockSize) #0 {
entry:
%cmp5 = icmp eq i32 %blockSize, 0
br i1 %cmp5, label %while.end, label %while.body.preheader
while.body.preheader: ; preds = %entry
%min.iters.check = icmp ult i32 %blockSize, 4
br i1 %min.iters.check, label %while.body.preheader19, label %vector.memcheck
vector.memcheck: ; preds = %while.body.preheader
%scevgep = getelementptr float, ptr %pDst, i32 %blockSize
%scevgep12 = getelementptr float, ptr %pSrc, i32 %blockSize
%bound0 = icmp ugt ptr %scevgep12, %pDst
%bound1 = icmp ugt ptr %scevgep, %pSrc
%found.conflict = and i1 %bound0, %bound1
%0 = lshr i32 %blockSize, 2
%1 = shl nuw i32 %0, 2
%2 = add i32 %1, -4
%3 = lshr i32 %2, 2
%4 = add nuw nsw i32 %3, 1
br i1 %found.conflict, label %while.body.preheader19, label %vector.ph
vector.ph: ; preds = %vector.memcheck
%n.vec = and i32 %blockSize, -4
%ind.end = sub i32 %blockSize, %n.vec
%ind.end15 = getelementptr float, ptr %pSrc, i32 %n.vec
%ind.end17 = getelementptr float, ptr %pDst, i32 %n.vec
%scevgep9 = getelementptr float, ptr %pDst, i32 -4
%scevgep14 = getelementptr float, ptr %pSrc, i32 -4
%start1 = call i32 @llvm.start.loop.iterations.i32(i32 %4)
br label %vector.body
vector.body: ; preds = %vector.body, %vector.ph
%lsr.iv15 = phi ptr [ %scevgep16, %vector.body ], [ %scevgep14, %vector.ph ]
%lsr.iv10 = phi ptr [ %scevgep11, %vector.body ], [ %scevgep9, %vector.ph ]
%5 = phi i32 [ %start1, %vector.ph ], [ %7, %vector.body ]
%scevgep18 = getelementptr <4 x float>, ptr %lsr.iv15, i32 1
%wide.load = load <4 x float>, ptr %scevgep18, align 4
%6 = call fast <4 x float> @llvm.fabs.v4f32(<4 x float> %wide.load)
%scevgep13 = getelementptr <4 x float>, ptr %lsr.iv10, i32 1
store <4 x float> %6, ptr %scevgep13, align 4
%scevgep11 = getelementptr float, ptr %lsr.iv10, i32 4
%scevgep16 = getelementptr float, ptr %lsr.iv15, i32 4
%7 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %5, i32 1)
%8 = icmp ne i32 %7, 0
br i1 %8, label %vector.body, label %middle.block
middle.block: ; preds = %vector.body
%cmp.n = icmp eq i32 %n.vec, %blockSize
br i1 %cmp.n, label %while.end, label %while.body.preheader19
while.body.preheader19: ; preds = %middle.block, %vector.memcheck, %while.body.preheader
%blkCnt.08.ph = phi i32 [ %blockSize, %vector.memcheck ], [ %blockSize, %while.body.preheader ], [ %ind.end, %middle.block ]
%pSrc.addr.07.ph = phi ptr [ %pSrc, %vector.memcheck ], [ %pSrc, %while.body.preheader ], [ %ind.end15, %middle.block ]
%pDst.addr.06.ph = phi ptr [ %pDst, %vector.memcheck ], [ %pDst, %while.body.preheader ], [ %ind.end17, %middle.block ]
%scevgep1 = getelementptr float, ptr %pSrc.addr.07.ph, i32 -1
%scevgep4 = getelementptr float, ptr %pDst.addr.06.ph, i32 -1
%start2 = call i32 @llvm.start.loop.iterations.i32(i32 %blkCnt.08.ph)
br label %while.body
while.body: ; preds = %while.body, %while.body.preheader19
%lsr.iv5 = phi ptr [ %scevgep6, %while.body ], [ %scevgep4, %while.body.preheader19 ]
%lsr.iv = phi ptr [ %scevgep2, %while.body ], [ %scevgep1, %while.body.preheader19 ]
%9 = phi i32 [ %start2, %while.body.preheader19 ], [ %12, %while.body ]
%scevgep3 = getelementptr float, ptr %lsr.iv, i32 1
%scevgep7 = getelementptr float, ptr %lsr.iv5, i32 1
%10 = load float, ptr %scevgep3, align 4
%11 = tail call fast float @llvm.fabs.f32(float %10)
store float %11, ptr %scevgep7, align 4
%scevgep2 = getelementptr float, ptr %lsr.iv, i32 1
%scevgep6 = getelementptr float, ptr %lsr.iv5, i32 1
%12 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %9, i32 1)
%13 = icmp ne i32 %12, 0
br i1 %13, label %while.body, label %while.end
while.end: ; preds = %while.body, %middle.block, %entry
ret void
}
declare float @llvm.fabs.f32(float)
declare <4 x float> @llvm.fabs.v4f32(<4 x float>)
declare i32 @llvm.start.loop.iterations.i32(i32)
declare i32 @llvm.loop.decrement.reg.i32.i32.i32(i32, i32)
...
---
name: remove_mov_lr_chain
alignment: 2
exposesReturnsTwice: false
legalized: false
regBankSelected: false
selected: false
failedISel: false
tracksRegLiveness: true
hasWinCFI: false
registers: []
liveins:
- { reg: '$r0', virtual-reg: '' }
- { reg: '$r1', virtual-reg: '' }
- { reg: '$r2', virtual-reg: '' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
hasStackMap: false
hasPatchPoint: false
stackSize: 16
offsetAdjustment: 0
maxAlignment: 4
adjustsStack: false
hasCalls: false
stackProtector: ''
maxCallFrameSize: 0
cvBytesOfCalleeSavedRegisters: 0
hasOpaqueSPAdjustment: false
hasVAStart: false
hasMustTailInVarArgFunc: false
localFrameSize: 0
savePoint: ''
restorePoint: ''
fixedStack: []
stack:
- { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,
stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false,
debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
- { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,
stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true,
debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
- { id: 2, name: '', type: spill-slot, offset: -12, size: 4, alignment: 4,
stack-id: default, callee-saved-register: '$r5', callee-saved-restored: true,
debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
- { id: 3, name: '', type: spill-slot, offset: -16, size: 4, alignment: 4,
stack-id: default, callee-saved-register: '$r4', callee-saved-restored: true,
debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
callSites: []
constants: []
machineFunctionInfo: {}
body: |
; CHECK-LABEL: name: remove_mov_lr_chain
; CHECK: bb.0.entry:
; CHECK-NEXT: successors: %bb.9(0x30000000), %bb.1(0x50000000)
; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r4, $r5, $r7
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $r5, killed $r7, killed $lr, implicit-def $sp, implicit $sp
; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 16
; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -4
; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r7, -8
; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r5, -12
; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r4, -16
; CHECK-NEXT: tCMPi8 renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr
; CHECK-NEXT: tBcc %bb.9, 0 /* CC::eq */, killed $cpsr
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.1.while.body.preheader:
; CHECK-NEXT: successors: %bb.6(0x40000000), %bb.2(0x40000000)
; CHECK-NEXT: liveins: $r0, $r1, $r2
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: tCMPi8 renamable $r2, 4, 14 /* CC::al */, $noreg, implicit-def $cpsr
; CHECK-NEXT: tBcc %bb.6, 3 /* CC::lo */, killed $cpsr
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2.vector.memcheck:
; CHECK-NEXT: successors: %bb.3(0x40000000), %bb.6(0x40000000)
; CHECK-NEXT: liveins: $r0, $r1, $r2
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: renamable $r3 = t2ADDrs renamable $r0, renamable $r2, 18, 14 /* CC::al */, $noreg, $noreg
; CHECK-NEXT: tCMPr killed renamable $r3, renamable $r1, 14 /* CC::al */, $noreg, implicit-def $cpsr
; CHECK-NEXT: t2IT 8, 4, implicit-def $itstate
; CHECK-NEXT: renamable $r3 = t2ADDrs renamable $r1, renamable $r2, 18, 8 /* CC::hi */, $cpsr, $noreg, implicit $itstate
; CHECK-NEXT: tCMPr killed renamable $r3, renamable $r0, 8 /* CC::hi */, killed $cpsr, implicit-def $cpsr, implicit killed $itstate
; CHECK-NEXT: tBcc %bb.6, 8 /* CC::hi */, killed $cpsr
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.3.vector.ph:
; CHECK-NEXT: successors: %bb.4(0x80000000)
; CHECK-NEXT: liveins: $r0, $r1, $r2
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: renamable $r4 = t2BICri renamable $r2, 3, 14 /* CC::al */, $noreg, $noreg
; CHECK-NEXT: renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg
; CHECK-NEXT: renamable $r12 = t2SUBri renamable $r4, 4, 14 /* CC::al */, $noreg, $noreg
; CHECK-NEXT: renamable $r7, dead $cpsr = tSUBrr renamable $r2, renamable $r4, 14 /* CC::al */, $noreg
; CHECK-NEXT: renamable $r3 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg
; CHECK-NEXT: renamable $r12 = t2ADDrs renamable $r0, renamable $r4, 18, 14 /* CC::al */, $noreg, $noreg
; CHECK-NEXT: dead $lr = tMOVr renamable $r3, 14 /* CC::al */, $noreg
; CHECK-NEXT: renamable $r0, dead $cpsr = tSUBi8 killed renamable $r0, 16, 14 /* CC::al */, $noreg
; CHECK-NEXT: $r5 = tMOVr killed $r3, 14 /* CC::al */, $noreg
; CHECK-NEXT: renamable $r3 = t2ADDrs renamable $r1, renamable $r4, 18, 14 /* CC::al */, $noreg, $noreg
; CHECK-NEXT: renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 16, 14 /* CC::al */, $noreg
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.4.vector.body:
; CHECK-NEXT: successors: %bb.4(0x7c000000), %bb.5(0x04000000)
; CHECK-NEXT: liveins: $r0, $r1, $r2, $r3, $r4, $r5, $r7, $r12
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: renamable $r0, renamable $q0 = MVE_VLDRWU32_pre killed renamable $r0, 16, 0, $noreg, $noreg :: (load (s128) from %ir.scevgep18, align 4)
; CHECK-NEXT: $lr = tMOVr killed $r5, 14 /* CC::al */, $noreg
; CHECK-NEXT: renamable $q0 = nnan ninf nsz arcp contract afn reassoc MVE_VABSf32 killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0
; CHECK-NEXT: renamable $r1 = MVE_VSTRBU8_pre killed renamable $q0, killed renamable $r1, 16, 0, $noreg, $noreg :: (store (s128) into %ir.scevgep13, align 4)
; CHECK-NEXT: renamable $lr = t2SUBri killed renamable $lr, 1, 14 /* CC::al */, $noreg, def $cpsr
; CHECK-NEXT: $r5 = tMOVr killed $lr, 14 /* CC::al */, $noreg
; CHECK-NEXT: tBcc %bb.4, 1 /* CC::ne */, killed $cpsr
; CHECK-NEXT: tB %bb.5, 14 /* CC::al */, $noreg
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.5.middle.block:
; CHECK-NEXT: successors: %bb.7(0x80000000)
; CHECK-NEXT: liveins: $r2, $r3, $r4, $r7, $r12
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: tCMPr killed renamable $r4, killed renamable $r2, 14 /* CC::al */, $noreg, implicit-def $cpsr
; CHECK-NEXT: $lr = tMOVr killed $r7, 14 /* CC::al */, $noreg
; CHECK-NEXT: t2IT 0, 8, implicit-def $itstate
; CHECK-NEXT: tPOP_RET 0 /* CC::eq */, killed $cpsr, def $r4, def $r5, def $r7, def $pc, implicit killed $itstate
; CHECK-NEXT: tB %bb.7, 14 /* CC::al */, $noreg
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.6:
; CHECK-NEXT: successors: %bb.7(0x80000000)
; CHECK-NEXT: liveins: $r0, $r1, $r2
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: $lr = tMOVr killed $r2, 14 /* CC::al */, $noreg
; CHECK-NEXT: $r12 = tMOVr killed $r0, 14 /* CC::al */, $noreg
; CHECK-NEXT: $r3 = tMOVr killed $r1, 14 /* CC::al */, $noreg
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.7.while.body.preheader19:
; CHECK-NEXT: successors: %bb.8(0x80000000)
; CHECK-NEXT: liveins: $lr, $r3, $r12
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: renamable $r0, dead $cpsr = tSUBi3 killed renamable $r3, 4, 14 /* CC::al */, $noreg
; CHECK-NEXT: renamable $r1 = t2SUBri killed renamable $r12, 4, 14 /* CC::al */, $noreg, $noreg
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.8.while.body:
; CHECK-NEXT: successors: %bb.8(0x7c000000), %bb.9(0x04000000)
; CHECK-NEXT: liveins: $lr, $r0, $r1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: renamable $s0 = VLDRS renamable $r1, 1, 14 /* CC::al */, $noreg :: (load (s32) from %ir.scevgep3)
; CHECK-NEXT: renamable $r1, dead $cpsr = tADDi8 killed renamable $r1, 4, 14 /* CC::al */, $noreg
; CHECK-NEXT: renamable $s0 = nnan ninf nsz arcp contract afn reassoc VABSS killed renamable $s0, 14 /* CC::al */, $noreg
; CHECK-NEXT: VSTRS killed renamable $s0, renamable $r0, 1, 14 /* CC::al */, $noreg :: (store (s32) into %ir.scevgep7)
; CHECK-NEXT: renamable $r0, dead $cpsr = tADDi8 killed renamable $r0, 4, 14 /* CC::al */, $noreg
; CHECK-NEXT: $lr = t2LEUpdate killed renamable $lr, %bb.8
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.9.while.end:
; CHECK-NEXT: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $r5, def $r7, def $pc
bb.0.entry:
successors: %bb.9(0x30000000), %bb.1(0x50000000)
liveins: $r0, $r1, $r2, $r4, $r5, $r7, $lr
frame-setup tPUSH 14, $noreg, killed $r4, killed $r5, killed $r7, killed $lr, implicit-def $sp, implicit $sp
frame-setup CFI_INSTRUCTION def_cfa_offset 16
frame-setup CFI_INSTRUCTION offset $lr, -4
frame-setup CFI_INSTRUCTION offset $r7, -8
frame-setup CFI_INSTRUCTION offset $r5, -12
frame-setup CFI_INSTRUCTION offset $r4, -16
tCMPi8 renamable $r2, 0, 14, $noreg, implicit-def $cpsr
tBcc %bb.9, 0, killed $cpsr
bb.1.while.body.preheader:
successors: %bb.6(0x40000000), %bb.2(0x40000000)
liveins: $r0, $r1, $r2
tCMPi8 renamable $r2, 4, 14, $noreg, implicit-def $cpsr
tBcc %bb.6, 3, killed $cpsr
bb.2.vector.memcheck:
successors: %bb.3(0x40000000), %bb.6(0x40000000)
liveins: $r0, $r1, $r2
renamable $r3 = t2ADDrs renamable $r0, renamable $r2, 18, 14, $noreg, $noreg
tCMPr killed renamable $r3, renamable $r1, 14, $noreg, implicit-def $cpsr
t2IT 8, 4, implicit-def $itstate
renamable $r3 = t2ADDrs renamable $r1, renamable $r2, 18, 8, $cpsr, $noreg, implicit $itstate
tCMPr killed renamable $r3, renamable $r0, 8, killed $cpsr, implicit-def $cpsr, implicit killed $itstate
tBcc %bb.6, 8, killed $cpsr
bb.3.vector.ph:
successors: %bb.4(0x80000000)
liveins: $r0, $r1, $r2
renamable $r4 = t2BICri renamable $r2, 3, 14, $noreg, $noreg
renamable $r3, dead $cpsr = tMOVi8 1, 14, $noreg
renamable $r12 = t2SUBri renamable $r4, 4, 14, $noreg, $noreg
renamable $r7, dead $cpsr = tSUBrr renamable $r2, renamable $r4, 14, $noreg
renamable $r3 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14, $noreg, $noreg
renamable $r12 = t2ADDrs renamable $r0, renamable $r4, 18, 14, $noreg, $noreg
$lr = t2DoLoopStart renamable $r3
renamable $r0, dead $cpsr = tSUBi8 killed renamable $r0, 16, 14, $noreg
$r5 = tMOVr killed $r3, 14, $noreg
renamable $r3 = t2ADDrs renamable $r1, renamable $r4, 18, 14, $noreg, $noreg
renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 16, 14, $noreg
bb.4.vector.body:
successors: %bb.4(0x7c000000), %bb.5(0x04000000)
liveins: $r0, $r1, $r2, $r3, $r4, $r5, $r7, $r12
renamable $r0, renamable $q0 = MVE_VLDRWU32_pre killed renamable $r0, 16, 0, $noreg, $noreg :: (load (s128) from %ir.scevgep18, align 4)
$lr = tMOVr killed $r5, 14, $noreg
renamable $q0 = nnan ninf nsz arcp contract afn reassoc MVE_VABSf32 killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0
renamable $r1 = MVE_VSTRBU8_pre killed renamable $q0, killed renamable $r1, 16, 0, $noreg, $noreg :: (store (s128) into %ir.scevgep13, align 4)
renamable $lr = t2LoopDec killed renamable $lr, 1
$r5 = tMOVr $lr, 14, $noreg
t2LoopEnd killed renamable $lr, %bb.4, implicit-def dead $cpsr
tB %bb.5, 14, $noreg
bb.5.middle.block:
successors: %bb.7(0x80000000)
liveins: $r2, $r3, $r4, $r7, $r12
tCMPr killed renamable $r4, killed renamable $r2, 14, $noreg, implicit-def $cpsr
$lr = tMOVr killed $r7, 14, $noreg
t2IT 0, 8, implicit-def $itstate
tPOP_RET 0, killed $cpsr, def $r4, def $r5, def $r7, def $pc, implicit killed $itstate
tB %bb.7, 14, $noreg
bb.6:
successors: %bb.7(0x80000000)
liveins: $r0, $r1, $r2
$lr = tMOVr killed $r2, 14, $noreg
$r12 = tMOVr killed $r0, 14, $noreg
$r3 = tMOVr killed $r1, 14, $noreg
bb.7.while.body.preheader19:
successors: %bb.8(0x80000000)
liveins: $lr, $r3, $r12
renamable $r0, dead $cpsr = tSUBi3 killed renamable $r3, 4, 14, $noreg
renamable $r1 = t2SUBri killed renamable $r12, 4, 14, $noreg, $noreg
$lr = t2DoLoopStart renamable $lr
bb.8.while.body:
successors: %bb.8(0x7c000000), %bb.9(0x04000000)
liveins: $lr, $r0, $r1
renamable $s0 = VLDRS renamable $r1, 1, 14, $noreg :: (load (s32) from %ir.scevgep3)
renamable $r1, dead $cpsr = tADDi8 killed renamable $r1, 4, 14, $noreg
renamable $s0 = nnan ninf nsz arcp contract afn reassoc VABSS killed renamable $s0, 14, $noreg
VSTRS killed renamable $s0, renamable $r0, 1, 14, $noreg :: (store (s32) into %ir.scevgep7)
renamable $r0, dead $cpsr = tADDi8 killed renamable $r0, 4, 14, $noreg
renamable $lr = t2LoopDec killed renamable $lr, 1
t2LoopEnd renamable $lr, %bb.8, implicit-def dead $cpsr
tB %bb.9, 14, $noreg
bb.9.while.end:
tPOP_RET 14, $noreg, def $r4, def $r5, def $r7, def $pc
...
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