This file is a partial list of people who have contributed to the LLVM
project. If you have contributed a patch or made some other contribution to
LLVM, please submit a patch to this file to add yourself, and it will be
done!
The list is sorted by surname and formatted to allow easy grepping and
beautification by scripts. The fields are: name (N), email (E), web-address
(W), PGP key ID and fingerprint (P), description (D), snail-mail address
(S), and (I) IRC handle.
N: Vikram Adve
E: [email protected]
W: http://www.cs.uiuc.edu/~vadve/
D: The Sparc64 backend, provider of much wisdom, and motivator for LLVM
N: Owen Anderson
E: [email protected]
D: LCSSA pass and related LoopUnswitch work
D: GVNPRE pass, DataLayout refactoring, random improvements
N: Henrik Bach
D: MingW Win32 API portability layer
N: Aaron Ballman
E: [email protected]
D: Clang frontend, frontend attributes, Windows support, general bug fixing
I: AaronBallman
N: Alexey Bataev
E: [email protected]
D: Clang frontend, OpenMP in clang, SLP vectorizer, Loop vectorizer, InstCombine
I: ABataev
N: Nate Begeman
E: [email protected]
D: PowerPC backend developer
D: Target-independent code generator and analysis improvements
N: Daniel Berlin
E: [email protected]
D: ET-Forest implementation.
D: Sparse bitmap
N: Geoff Berry
E: [email protected]
E: [email protected]
D: AArch64 backend improvements
D: Added EarlyCSE MemorySSA support
D: CodeGen improvements
N: David Blaikie
E: [email protected]
D: General bug fixing/fit & finish, mostly in Clang
N: Neil Booth
E: [email protected]
D: APFloat implementation.
N: Alex Bradbury
E: [email protected]
D: RISC-V backend
N: Misha Brukman
E: [email protected]
W: http://misha.brukman.net
D: Portions of X86 and Sparc JIT compilers, PowerPC backend
D: Incremental bitcode loader
N: Cameron Buschardt
E: [email protected]
D: The `mem2reg' pass - promotes values stored in memory to registers
N: Brendon Cahoon
E: [email protected]
D: Loop unrolling with run-time trip counts.
N: Chandler Carruth
E: [email protected]
E: [email protected]
D: Hashing algorithms and interfaces
D: Inline cost analysis
D: Machine block placement pass
D: SROA
N: Casey Carter
E: [email protected]
D: Fixes to the Reassociation pass, various improvement patches
N: Evan Cheng
E: [email protected]
D: ARM and X86 backends
D: Instruction scheduler improvements
D: Register allocator improvements
D: Loop optimizer improvements
D: Target-independent code generator improvements
N: Dan Villiom Podlaski Christiansen
E: [email protected]
E: [email protected]
W: http://villiom.dk
D: LLVM Makefile improvements
D: Clang diagnostic & driver tweaks
S: Aarhus, Denmark
N: Jeff Cohen
E: [email protected]
W: http://jolt-lang.org
D: Native Win32 API portability layer
N: John T. Criswell
E: [email protected]
D: Original Autoconf support, documentation improvements, bug fixes
N: Anshuman Dasgupta
E: [email protected]
D: Deterministic finite automaton based infrastructure for VLIW packetization
N: Stefanus Du Toit
E: [email protected]
D: Bug fixes and minor improvements
N: Rafael Avila de Espindola
E: [email protected]
D: MC and LLD work
N: Dave Estes
E: [email protected]
D: AArch64 machine description for Cortex-A53
N: Alkis Evlogimenos
E: [email protected]
D: Linear scan register allocator, many codegen improvements, Java frontend
N: Hal Finkel
E: [email protected]
D: Basic-block autovectorization, PowerPC backend improvements
N: Eric Fiselier
E: [email protected]
D: LIT patches and documentation
N: Ryan Flynn
E: [email protected]
D: Miscellaneous bug fixes
N: Brian Gaeke
E: [email protected]
W: http://www.students.uiuc.edu/~gaeke/
D: Portions of X86 static and JIT compilers; initial SparcV8 backend
D: Dynamic trace optimizer
D: FreeBSD/X86 compatibility fixes, the llvm-nm tool
N: Nicolas Geoffray
E: [email protected]
W: http://www-src.lip6.fr/homepages/Nicolas.Geoffray/
D: PPC backend fixes for Linux
N: Louis Gerbarg
E: [email protected]
D: Portions of the PowerPC backend
N: Saem Ghani
E: [email protected]
D: Callgraph class cleanups
N: Mikhail Glushenkov
E: [email protected]
D: Author of llvmc2
N: Dan Gohman
E: [email protected]
D: Miscellaneous bug fixes
D: WebAssembly Backend
N: Renato Golin
E: [email protected]
E: [email protected]
D: ARM/AArch64 back-end improvements
D: Loop Vectorizer improvements
D: Regression and Test Suite improvements
D: Linux compatibility (GNU, musl, etc)
D: Initial Linux kernel / Android support effort
I: rengolin
N: David Goodwin
E: [email protected]
D: Thumb-2 code generator
N: David Greene
E: [email protected]
D: Miscellaneous bug fixes
D: Register allocation refactoring
N: Gabor Greif
E: [email protected]
D: Improvements for space efficiency
N: James Grosbach
E: [email protected]
I: grosbach
D: SjLj exception handling support
D: General fixes and improvements for the ARM back-end
D: MCJIT
D: ARM integrated assembler and assembly parser
D: Led effort for the backend formerly known as ARM64
N: Lang Hames
E: [email protected]
D: PBQP-based register allocator
N: Gordon Henriksen
E: [email protected]
D: Pluggable GC support
D: C interface
D: Ocaml bindings
N: Raul Fernandes Herbster
E: [email protected]
D: JIT support for ARM
N: Paolo Invernizzi
E: [email protected]
D: Visual C++ compatibility fixes
N: Patrick Jenkins
E: [email protected]
D: Nightly Tester
N: Tony(Yanjun) Jiang
E: [email protected]
D: PowerPC Backend Developer
D: Improvements to the PPC backend and miscellaneous bug fixes
N: Dale Johannesen
E: [email protected]
D: ARM constant islands improvements
D: Tail merging improvements
D: Rewrite X87 back end
D: Use APFloat for floating point constants widely throughout compiler
D: Implement X87 long double
N: Brad Jones
E: [email protected]
D: Support for packed types
N: Rod Kay
E: [email protected]
D: Author of LLVM Ada bindings
N: Erich Keane
E: [email protected]
D: A variety of Clang contributions including function multiversioning, regcall/vectorcall.
I: ErichKeane
N: Eric Kidd
W: http://randomhacks.net/
D: llvm-config script
N: Anton Korobeynikov
E: anton at korobeynikov dot info
D: Mingw32 fixes, cross-compiling support, stdcall/fastcall calling conv.
D: x86/linux PIC codegen, aliases, regparm/visibility attributes
D: Switch lowering refactoring
N: Sumant Kowshik
E: [email protected]
D: Author of the original C backend
N: Benjamin Kramer
E: [email protected]
D: Miscellaneous bug fixes
N: Michael Kuperstein
E: [email protected]
D: Loop Vectorizer
N: Sundeep Kushwaha
E: [email protected]
D: Implemented DFA-based target independent VLIW packetizer
N: Christopher Lamb
E: [email protected]
D: aligned load/store support, parts of noalias and restrict support
D: vreg subreg infrastructure, X86 codegen improvements based on subregs
D: address spaces
N: Jim Laskey
E: [email protected]
D: Improvements to the PPC backend, instruction scheduling
D: Debug and Dwarf implementation
D: Auto upgrade mangler
D: llvm-gcc4 svn wrangler
N: Chris Lattner
E: [email protected]
W: http://nondot.org/~sabre/
D: Primary architect of LLVM
N: Tanya Lattner (Tanya Brethour)
E: [email protected]
W: http://nondot.org/~tonic/
D: The initial llvm-ar tool, converted regression testsuite to dejagnu
D: Modulo scheduling in the SparcV9 backend
D: Release manager (1.7+)
N: Sylvestre Ledru
E: [email protected]
W: http://sylvestre.ledru.info/
W: https://apt.llvm.org/
D: Debian and Ubuntu packaging
D: Continuous integration with jenkins
N: Andrew Lenharth
E: [email protected]
W: http://www.lenharth.org/~andrewl/
D: Alpha backend
D: Sampling based profiling
N: Nick Lewycky
E: [email protected]
D: PredicateSimplifier pass
N: Tony Linthicum, et. al.
E: [email protected]
D: Backend for Qualcomm's Hexagon VLIW processor.
N: Bruno Cardoso Lopes
E: [email protected]
I: bruno
W: http://brunocardoso.cc
D: Mips backend
D: Random ARM integrated assembler and assembly parser improvements
D: General X86 AVX1 support
N: Weining Lu
E: [email protected]
D: LoongArch backend
N: Duraid Madina
E: [email protected]
W: http://kinoko.c.u-tokyo.ac.jp/~duraid/
D: IA64 backend, BigBlock register allocator
N: John McCall
E: [email protected]
D: Clang semantic analysis and IR generation
N: Michael McCracken
E: [email protected]
D: Line number support for llvmgcc
N: Fanbo Meng
E: [email protected]
D: z/OS support
N: Vladimir Merzliakov
E: [email protected]
D: Test suite fixes for FreeBSD
N: Scott Michel
E: [email protected]
D: Added STI Cell SPU backend.
N: Kai Nacke
E: [email protected]
D: Support for implicit TLS model used with MS VC runtime
D: Dumping of Win64 EH structures
N: Takumi Nakamura
I: chapuni
E: [email protected]
E: [email protected]
D: Maintaining the Git monorepo
W: https://github.com/llvm-project/
S: Ebina, Japan
N: Edward O'Callaghan
E: [email protected]
W: http://www.auroraux.org
D: Add Clang support with various other improvements to utils/NewNightlyTest.pl
D: Fix and maintain Solaris & AuroraUX support for llvm, various build warnings
D: and error clean ups.
N: Morten Ofstad
E: [email protected]
D: Visual C++ compatibility fixes
N: Jakob Stoklund Olesen
E: [email protected]
D: Machine code verifier
D: Blackfin backend
D: Fast register allocator
D: Greedy register allocator
N: Richard Osborne
E: [email protected]
D: XCore backend
N: Piotr Padlewski
E: [email protected]
D: !invariant.group metadata and other intrinsics for devirtualization in clang
N: Devang Patel
E: [email protected]
D: LTO tool, PassManager rewrite, Loop Pass Manager, Loop Rotate
D: GCC PCH Integration (llvm-gcc), llvm-gcc improvements
D: Optimizer improvements, Loop Index Split
N: Ana Pazos
E: [email protected]
D: Fixes and improvements to the AArch64 backend
N: Wesley Peck
E: [email protected]
W: http://wesleypeck.com/
D: MicroBlaze backend
N: Francois Pichet
E: [email protected]
D: MSVC support
N: Simon Pilgrim
E: [email protected]
D: X86 backend, Selection DAG, Scheduler Models and Cost Tables.
N: Adrian Prantl
E: [email protected]
D: Debug Information
N: Vladimir Prus
W: http://vladimir_prus.blogspot.com
E: [email protected]
D: Made inst_iterator behave like a proper iterator, LowerConstantExprs pass
N: Kalle Raiskila
E: [email protected]
D: Some bugfixes to CellSPU
N: Xerxes Ranby
E: [email protected]
D: Cmake dependency chain and various bug fixes
N: Alex Rosenberg
E: [email protected]
I: arosenberg
D: ARM calling conventions rewrite, hard float support
N: Chad Rosier
E: [email protected]
I: mcrosier
D: AArch64 fast instruction selection pass
D: Fixes and improvements to the ARM fast-isel pass
D: Fixes and improvements to the AArch64 backend
N: Nadav Rotem
E: [email protected]
D: X86 code generation improvements, Loop Vectorizer, SLP Vectorizer
N: Roman Samoilov
E: [email protected]
D: MSIL backend
N: Duncan Sands
E: [email protected]
I: baldrick
D: Ada support in llvm-gcc
D: Dragonegg plugin
D: Exception handling improvements
D: Type legalizer rewrite
N: Ruchira Sasanka
E: [email protected]
D: Graph coloring register allocator for the Sparc64 backend
N: Alina Sbirlea
E: [email protected]
D: MemorySSA, BatchAA, misc loop and new pass manager work.
N: Arnold Schwaighofer
E: [email protected]
D: Tail call optimization for the x86 backend
N: Shantonu Sen
E: [email protected]
D: Miscellaneous bug fixes
N: Anand Shukla
E: [email protected]
D: The `paths' pass
N: Michael J. Spencer
E: [email protected]
D: Shepherding Windows COFF support into MC.
D: Lots of Windows stuff.
N: Reid Spencer
E: [email protected]
W: http://reidspencer.com/
D: Lots of stuff, see: http://wiki.llvm.org/index.php/User:Reid
N: Abhina Sreeskantharajan
E: [email protected]
D: z/OS support
N: Alp Toker
E: [email protected]
W: http://atoker.com/
D: C++ frontend next generation standards implementation
N: Craig Topper
E: [email protected]
D: X86 codegen and disassembler improvements. AVX2 support.
N: Edwin Torok
E: [email protected]
D: Miscellaneous bug fixes
N: Adam Treat
E: [email protected]
D: C++ bugs filed, and C++ front-end bug fixes.
N: Andrew Trick
E: [email protected]
D: Instruction Scheduling, ...
N: Lauro Ramos Venancio
E: [email protected]
D: ARM backend improvements
D: Thread Local Storage implementation
N: Phoebe Wang
E: [email protected]
D: X86 bug fixes and new instruction support.
N: Bill Wendling
I: wendling
E: [email protected]
D: Release manager, IR Linker, LTO.
D: Bunches of stuff.
N: Bob Wilson
E: [email protected]
D: Advanced SIMD (NEON) support in the ARM backend.
N: QingShan Zhang
N: steven.zhang
E: [email protected]
N: Li Jia He
E: [email protected]
D: PowerPC Backend Developer
N: Zi Xuan Wu
N: Zeson
E: [email protected]
N: Kang Zhang
E: [email protected]
D: PowerPC Backend Developer
N: Zheng Chen
E: [email protected]
D: PowerPC Backend Developer
N: Djordje Todorovic
E: [email protected]
D: Debug Information
N: Biplob Mishra
E: [email protected]
D: PowerPC Analysis
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