//===-- X86DisassemblerDecoderCommon.h - Disassembler decoder ---*- C++ -*-===// // // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// // // This file is part of the X86 Disassembler. // It contains common definitions used by both the disassembler and the table // generator. // Documentation for the disassembler can be found in X86Disassembler.h. // //===----------------------------------------------------------------------===// #ifndef LLVM_SUPPORT_X86DISASSEMBLERDECODERCOMMON_H #define LLVM_SUPPORT_X86DISASSEMBLERDECODERCOMMON_H #include "llvm/Support/DataTypes.h" namespace llvm { namespace X86Disassembler { #define INSTRUCTIONS_SYM … #define CONTEXTS_SYM … #define ONEBYTE_SYM … #define TWOBYTE_SYM … #define THREEBYTE38_SYM … #define THREEBYTE3A_SYM … #define XOP8_MAP_SYM … #define XOP9_MAP_SYM … #define XOPA_MAP_SYM … #define THREEDNOW_MAP_SYM … #define MAP4_SYM … #define MAP5_SYM … #define MAP6_SYM … #define MAP7_SYM … #define INSTRUCTIONS_STR … #define CONTEXTS_STR … #define ONEBYTE_STR … #define TWOBYTE_STR … #define THREEBYTE38_STR … #define THREEBYTE3A_STR … #define XOP8_MAP_STR … #define XOP9_MAP_STR … #define XOPA_MAP_STR … #define THREEDNOW_MAP_STR … #define MAP4_STR … #define MAP5_STR … #define MAP6_STR … #define MAP7_STR … // Attributes of an instruction that must be known before the opcode can be // processed correctly. Most of these indicate the presence of particular // prefixes, but ATTR_64BIT is simply an attribute of the decoding context. enum attributeBits { … }; // Combinations of the above attributes that are relevant to instruction // decode. Although other combinations are possible, they can be reduced to // these without affecting the ultimately decoded instruction. // Class name Rank Rationale for rank assignment #define INSTRUCTION_CONTEXTS … #define ENUM_ENTRY … enum InstructionContext { … }; #undef ENUM_ENTRY // Opcode types, which determine which decode table to use, both in the Intel // manual and also for the decoder. enum OpcodeType { … }; // The following structs are used for the hierarchical decode table. After // determining the instruction's class (i.e., which IC_* constant applies to // it), the decoder reads the opcode. Some instructions require specific // values of the ModR/M byte, so the ModR/M byte indexes into the final table. // // If a ModR/M byte is not required, "required" is left unset, and the values // for each instructionID are identical. InstrUID; // ModRMDecisionType - describes the type of ModR/M decision, allowing the // consumer to determine the number of entries in it. // // MODRM_ONEENTRY - No matter what the value of the ModR/M byte is, the decoded // instruction is the same. // MODRM_SPLITRM - If the ModR/M byte is between 0x00 and 0xbf, the opcode // corresponds to one instruction; otherwise, it corresponds to // a different instruction. // MODRM_SPLITMISC- If the ModR/M byte is between 0x00 and 0xbf, ModR/M byte // divided by 8 is used to select instruction; otherwise, each // value of the ModR/M byte could correspond to a different // instruction. // MODRM_SPLITREG - ModR/M byte divided by 8 is used to select instruction. This // corresponds to instructions that use reg field as opcode // MODRM_FULL - Potentially, each value of the ModR/M byte could correspond // to a different instruction. #define MODRMTYPES … #define ENUM_ENTRY … enum ModRMDecisionType { … }; #undef ENUM_ENTRY #define CASE_ENCODING_RM … #define CASE_ENCODING_VSIB … // Physical encodings of instruction operands. #define ENCODINGS … #define ENUM_ENTRY … enum OperandEncoding { … }; #undef ENUM_ENTRY // Semantic interpretations of instruction operands. #define TYPES … #define ENUM_ENTRY … enum OperandType { … }; #undef ENUM_ENTRY /// The specification for how to extract and interpret one operand. struct OperandSpecifier { … }; static const unsigned X86_MAX_OPERANDS = …; /// Decoding mode for the Intel disassembler. 16-bit, 32-bit, and 64-bit mode /// are supported, and represent real mode, IA-32e, and IA-32e in 64-bit mode, /// respectively. enum DisassemblerMode { … }; } // namespace X86Disassembler } // namespace llvm #endif
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