//===--- X86.cpp - Implement X86 target feature support -------------------===// // // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// // // This file implements X86 TargetInfo objects. // //===----------------------------------------------------------------------===// #include "X86.h" #include "clang/Basic/Builtins.h" #include "clang/Basic/Diagnostic.h" #include "clang/Basic/TargetBuiltins.h" #include "llvm/ADT/StringExtras.h" #include "llvm/ADT/StringRef.h" #include "llvm/ADT/StringSwitch.h" #include "llvm/TargetParser/X86TargetParser.h" #include <optional> namespace clang { namespace targets { static constexpr Builtin::Info BuiltinInfoX86[] = …; static const char *const GCCRegNames[] = …; const TargetInfo::AddlRegName AddlRegNames[] = …; } // namespace targets } // namespace clang usingnamespaceclang; usingnamespaceclang::targets; bool X86TargetInfo::setFPMath(StringRef Name) { … } bool X86TargetInfo::initFeatureMap( llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU, const std::vector<std::string> &FeaturesVec) const { … } void X86TargetInfo::setFeatureEnabled(llvm::StringMap<bool> &Features, StringRef Name, bool Enabled) const { … } /// handleTargetFeatures - Perform initialization based on the user /// configured set of features. bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features, DiagnosticsEngine &Diags) { … } /// X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro /// definitions for this particular subtarget. void X86TargetInfo::getTargetDefines(const LangOptions &Opts, MacroBuilder &Builder) const { … } bool X86TargetInfo::isValidFeatureName(StringRef Name) const { … } bool X86TargetInfo::hasFeature(StringRef Feature) const { … } // We can't use a generic validation scheme for the features accepted here // versus subtarget features accepted in the target attribute because the // bitfield structure that's initialized in the runtime only supports the // below currently rather than the full range of subtarget features. (See // X86TargetInfo::hasFeature for a somewhat comprehensive list). bool X86TargetInfo::validateCpuSupports(StringRef FeatureStr) const { … } static llvm::X86::ProcessorFeatures getFeature(StringRef Name) { … } unsigned X86TargetInfo::multiVersionSortPriority(StringRef Name) const { … } bool X86TargetInfo::validateCPUSpecificCPUDispatch(StringRef Name) const { … } char X86TargetInfo::CPUSpecificManglingCharacter(StringRef Name) const { … } void X86TargetInfo::getCPUSpecificCPUDispatchFeatures( StringRef Name, llvm::SmallVectorImpl<StringRef> &Features) const { … } // We can't use a generic validation scheme for the cpus accepted here // versus subtarget cpus accepted in the target attribute because the // variables intitialized by the runtime only support the below currently // rather than the full range of cpus. bool X86TargetInfo::validateCpuIs(StringRef FeatureStr) const { … } static unsigned matchAsmCCConstraint(const char *Name) { … } bool X86TargetInfo::validateAsmConstraint( const char *&Name, TargetInfo::ConstraintInfo &Info) const { … } // Below is based on the following information: // +------------------------------------+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ // | Processor Name | Cache Line Size (Bytes) | Source | // +------------------------------------+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ // | i386 | 64 | https://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-optimization-manual.pdf | // | i486 | 16 | "four doublewords" (doubleword = 32 bits, 4 bits * 32 bits = 16 bytes) https://en.wikichip.org/w/images/d/d3/i486_MICROPROCESSOR_HARDWARE_REFERENCE_MANUAL_%281990%29.pdf and http://citeseerx.ist.psu.edu/viewdoc/download?doi=10.1.1.126.4216&rep=rep1&type=pdf (page 29) | // | i586/Pentium MMX | 32 | https://www.7-cpu.com/cpu/P-MMX.html | // | i686/Pentium | 32 | https://www.7-cpu.com/cpu/P6.html | // | Netburst/Pentium4 | 64 | https://www.7-cpu.com/cpu/P4-180.html | // | Atom | 64 | https://www.7-cpu.com/cpu/Atom.html | // | Westmere | 64 | https://en.wikichip.org/wiki/intel/microarchitectures/sandy_bridge_(client) "Cache Architecture" | // | Sandy Bridge | 64 | https://en.wikipedia.org/wiki/Sandy_Bridge and https://www.7-cpu.com/cpu/SandyBridge.html | // | Ivy Bridge | 64 | https://blog.stuffedcow.net/2013/01/ivb-cache-replacement/ and https://www.7-cpu.com/cpu/IvyBridge.html | // | Haswell | 64 | https://www.7-cpu.com/cpu/Haswell.html | // | Broadwell | 64 | https://www.7-cpu.com/cpu/Broadwell.html | // | Skylake (including skylake-avx512) | 64 | https://www.nas.nasa.gov/hecc/support/kb/skylake-processors_550.html "Cache Hierarchy" | // | Cascade Lake | 64 | https://www.nas.nasa.gov/hecc/support/kb/cascade-lake-processors_579.html "Cache Hierarchy" | // | Skylake | 64 | https://en.wikichip.org/wiki/intel/microarchitectures/kaby_lake "Memory Hierarchy" | // | Ice Lake | 64 | https://www.7-cpu.com/cpu/Ice_Lake.html | // | Knights Landing | 64 | https://software.intel.com/en-us/articles/intel-xeon-phi-processor-7200-family-memory-management-optimizations "The Intel® Xeon Phi™ Processor Architecture" | // | Knights Mill | 64 | https://software.intel.com/sites/default/files/managed/9e/bc/64-ia-32-architectures-optimization-manual.pdf?countrylabel=Colombia "2.5.5.2 L1 DCache " | // +------------------------------------+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ std::optional<unsigned> X86TargetInfo::getCPUCacheLineSize() const { … } bool X86TargetInfo::validateOutputSize(const llvm::StringMap<bool> &FeatureMap, StringRef Constraint, unsigned Size) const { … } bool X86TargetInfo::validateInputSize(const llvm::StringMap<bool> &FeatureMap, StringRef Constraint, unsigned Size) const { … } bool X86TargetInfo::validateOperandSize(const llvm::StringMap<bool> &FeatureMap, StringRef Constraint, unsigned Size) const { … } std::string X86TargetInfo::convertConstraint(const char *&Constraint) const { … } void X86TargetInfo::fillValidCPUList(SmallVectorImpl<StringRef> &Values) const { … } void X86TargetInfo::fillValidTuneCPUList(SmallVectorImpl<StringRef> &Values) const { … } ArrayRef<const char *> X86TargetInfo::getGCCRegNames() const { … } ArrayRef<TargetInfo::AddlRegName> X86TargetInfo::getGCCAddlRegNames() const { … } ArrayRef<Builtin::Info> X86_32TargetInfo::getTargetBuiltins() const { … } ArrayRef<Builtin::Info> X86_64TargetInfo::getTargetBuiltins() const { … }
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