ISDOpcodes.h | Explore in Territory

//===-- llvm/CodeGen/ISDOpcodes.h - CodeGen opcodes -------------*- C++ -*-===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
//
// This file declares codegen opcodes and related utilities.
//
//===----------------------------------------------------------------------===//

#ifndef LLVM_CODEGEN_ISDOPCODES_H
#define LLVM_CODEGEN_ISDOPCODES_H

#include "llvm/CodeGen/ValueTypes.h"

namespace llvm {

/// ISD namespace - This namespace contains an enum which represents all of the
/// SelectionDAG node types and value types.
///
namespace ISD {

//===--------------------------------------------------------------------===//
/// ISD::NodeType enum - This enum defines the target-independent operators
/// for a SelectionDAG.
///
/// Targets may also define target-dependent operator codes for SDNodes. For
/// example, on x86, these are the enum values in the X86ISD namespace.
/// Targets should aim to use target-independent operators to model their
/// instruction sets as much as possible, and only use target-dependent
/// operators when they have special requirements.
///
/// Finally, during and after selection proper, SNodes may use special
/// operator codes that correspond directly with MachineInstr opcodes. These
/// are used to represent selected instructions. See the isMachineOpcode()
/// and getMachineOpcode() member functions of SDNode.
///
enum NodeType { … };

/// FIRST_TARGET_STRICTFP_OPCODE - Target-specific pre-isel operations
/// which cannot raise FP exceptions should be less than this value.
/// Those that do must not be less than this value.
static const int FIRST_TARGET_STRICTFP_OPCODE = …;

/// FIRST_TARGET_MEMORY_OPCODE - Target-specific pre-isel operations
/// which do not reference a specific memory location should be less than
/// this value. Those that do must not be less than this value, and can
/// be used with SelectionDAG::getMemIntrinsicNode.
static const int FIRST_TARGET_MEMORY_OPCODE = …;

/// Whether this is bitwise logic opcode.
inline bool isBitwiseLogicOp(unsigned Opcode) { … }

/// Get underlying scalar opcode for VECREDUCE opcode.
/// For example ISD::AND for ISD::VECREDUCE_AND.
NodeType getVecReduceBaseOpcode(unsigned VecReduceOpcode);

/// Whether this is a vector-predicated Opcode.
bool isVPOpcode(unsigned Opcode);

/// Whether this is a vector-predicated binary operation opcode.
bool isVPBinaryOp(unsigned Opcode);

/// Whether this is a vector-predicated reduction opcode.
bool isVPReduction(unsigned Opcode);

/// The operand position of the vector mask.
std::optional<unsigned> getVPMaskIdx(unsigned Opcode);

/// The operand position of the explicit vector length parameter.
std::optional<unsigned> getVPExplicitVectorLengthIdx(unsigned Opcode);

/// Translate this VP Opcode to its corresponding non-VP Opcode.
std::optional<unsigned> getBaseOpcodeForVP(unsigned Opcode, bool hasFPExcept);

/// Translate this non-VP Opcode to its corresponding VP Opcode.
std::optional<unsigned> getVPForBaseOpcode(unsigned Opcode);

//===--------------------------------------------------------------------===//
/// MemIndexedMode enum - This enum defines the load / store indexed
/// addressing modes.
///
/// UNINDEXED    "Normal" load / store. The effective address is already
///              computed and is available in the base pointer. The offset
///              operand is always undefined. In addition to producing a
///              chain, an unindexed load produces one value (result of the
///              load); an unindexed store does not produce a value.
///
/// PRE_INC      Similar to the unindexed mode where the effective address is
/// PRE_DEC      the value of the base pointer add / subtract the offset.
///              It considers the computation as being folded into the load /
///              store operation (i.e. the load / store does the address
///              computation as well as performing the memory transaction).
///              The base operand is always undefined. In addition to
///              producing a chain, pre-indexed load produces two values
///              (result of the load and the result of the address
///              computation); a pre-indexed store produces one value (result
///              of the address computation).
///
/// POST_INC     The effective address is the value of the base pointer. The
/// POST_DEC     value of the offset operand is then added to / subtracted
///              from the base after memory transaction. In addition to
///              producing a chain, post-indexed load produces two values
///              (the result of the load and the result of the base +/- offset
///              computation); a post-indexed store produces one value (the
///              the result of the base +/- offset computation).
enum MemIndexedMode { … };

static const int LAST_INDEXED_MODE = …;

//===--------------------------------------------------------------------===//
/// MemIndexType enum - This enum defines how to interpret MGATHER/SCATTER's
/// index parameter when calculating addresses.
///
/// SIGNED_SCALED     Addr = Base + ((signed)Index * Scale)
/// UNSIGNED_SCALED   Addr = Base + ((unsigned)Index * Scale)
///
/// NOTE: The value of Scale is typically only known to the node owning the
/// IndexType, with a value of 1 the equivalent of being unscaled.
enum MemIndexType { … };

static const int LAST_MEM_INDEX_TYPE = …;

inline bool isIndexTypeSigned(MemIndexType IndexType) { … }

//===--------------------------------------------------------------------===//
/// LoadExtType enum - This enum defines the three variants of LOADEXT
/// (load with extension).
///
/// SEXTLOAD loads the integer operand and sign extends it to a larger
///          integer result type.
/// ZEXTLOAD loads the integer operand and zero extends it to a larger
///          integer result type.
/// EXTLOAD  is used for two things: floating point extending loads and
///          integer extending loads [the top bits are undefined].
enum LoadExtType { … };

static const int LAST_LOADEXT_TYPE = …;

NodeType getExtForLoadExtType(bool IsFP, LoadExtType);

//===--------------------------------------------------------------------===//
/// ISD::CondCode enum - These are ordered carefully to make the bitfields
/// below work out, when considering SETFALSE (something that never exists
/// dynamically) as 0.  "U" -> Unsigned (for integer operands) or Unordered
/// (for floating point), "L" -> Less than, "G" -> Greater than, "E" -> Equal
/// to.  If the "N" column is 1, the result of the comparison is undefined if
/// the input is a NAN.
///
/// All of these (except for the 'always folded ops') should be handled for
/// floating point.  For integer, only the SETEQ,SETNE,SETLT,SETLE,SETGT,
/// SETGE,SETULT,SETULE,SETUGT, and SETUGE opcodes are used.
///
/// Note that these are laid out in a specific order to allow bit-twiddling
/// to transform conditions.
enum CondCode { … };

/// Return true if this is a setcc instruction that performs a signed
/// comparison when used with integer operands.
inline bool isSignedIntSetCC(CondCode Code) { … }

/// Return true if this is a setcc instruction that performs an unsigned
/// comparison when used with integer operands.
inline bool isUnsignedIntSetCC(CondCode Code) { … }

/// Return true if this is a setcc instruction that performs an equality
/// comparison when used with integer operands.
inline bool isIntEqualitySetCC(CondCode Code) { … }

/// Return true if this is a setcc instruction that performs an equality
/// comparison when used with floating point operands.
inline bool isFPEqualitySetCC(CondCode Code) { … }

/// Return true if the specified condition returns true if the two operands to
/// the condition are equal. Note that if one of the two operands is a NaN,
/// this value is meaningless.
inline bool isTrueWhenEqual(CondCode Cond) { … }

/// This function returns 0 if the condition is always false if an operand is
/// a NaN, 1 if the condition is always true if the operand is a NaN, and 2 if
/// the condition is undefined if the operand is a NaN.
inline unsigned getUnorderedFlavor(CondCode Cond) { … }

/// Return the operation corresponding to !(X op Y), where 'op' is a valid
/// SetCC operation.
CondCode getSetCCInverse(CondCode Operation, EVT Type);

inline bool isExtOpcode(unsigned Opcode) { … }

inline bool isExtVecInRegOpcode(unsigned Opcode) { … }

namespace GlobalISel {
/// Return the operation corresponding to !(X op Y), where 'op' is a valid
/// SetCC operation. The U bit of the condition code has different meanings
/// between floating point and integer comparisons and LLT's don't provide
/// this distinction. As such we need to be told whether the comparison is
/// floating point or integer-like. Pointers should use integer-like
/// comparisons.
CondCode getSetCCInverse(CondCode Operation, bool isIntegerLike);
} // end namespace GlobalISel

/// Return the operation corresponding to (Y op X) when given the operation
/// for (X op Y).
CondCode getSetCCSwappedOperands(CondCode Operation);

/// Return the result of a logical OR between different comparisons of
/// identical values: ((X op1 Y) | (X op2 Y)). This function returns
/// SETCC_INVALID if it is not possible to represent the resultant comparison.
CondCode getSetCCOrOperation(CondCode Op1, CondCode Op2, EVT Type);

/// Return the result of a logical AND between different comparisons of
/// identical values: ((X op1 Y) & (X op2 Y)). This function returns
/// SETCC_INVALID if it is not possible to represent the resultant comparison.
CondCode getSetCCAndOperation(CondCode Op1, CondCode Op2, EVT Type);

} // namespace ISD

} // namespace llvm

#endif
llvm/llvm/include/llvm/CodeGen/ISDOpcodes.h
