llvm/llvm/unittests/Target/AArch64/AArch64SVESchedPseudoTest.cpp

#include "AArch64InstrInfo.h"
#include "AArch64Subtarget.h"
#include "AArch64TargetMachine.h"
#include "llvm/MC/MCSubtargetInfo.h"
#include "llvm/MC/TargetRegistry.h"
#include "llvm/Support/TargetSelect.h"
#include "llvm/Support/raw_ostream.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetOptions.h"

#include "gtest/gtest.h"

#define GET_COMPUTE_FEATURES
#include "AArch64GenInstrInfo.inc"

usingnamespacellvm;
namespace {
std::unique_ptr<LLVMTargetMachine> createTargetMachine(const std::string &CPU) { … }

std::unique_ptr<AArch64InstrInfo> createInstrInfo(TargetMachine *TM) { … }

/// Returns true if the instruction is enabled under a feature that the
/// CPU supports.
static bool isInstructionSupportedByCPU(unsigned Opcode,
                                        FeatureBitset Features) { … }

void runSVEPseudoTestForCPU(const std::string &CPU) { … }

// TODO : Add more CPUs that support SVE/SVE2
TEST(AArch64SVESchedPseudoTesta510, IsCorrect) { … }

TEST(AArch64SVESchedPseudoTestn1, IsCorrect) { … }

TEST(AArch64SVESchedPseudoTestn3, IsCorrect) { … }

TEST(AArch64SVESchedPseudoTestv1, IsCorrect) { … }

TEST(AArch64SVESchedPseudoTestv2, IsCorrect) { … }

} // namespace