llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/render-vlop-rv64.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
# RUN: llc -mtriple=riscv64 -mattr=+v,+m -run-pass=instruction-select \
# RUN:   -verify-machineinstrs %s -o - | FileCheck %s

---
name:            negative_vl
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.1:
    ; CHECK-LABEL: name: negative_vl
    ; CHECK: [[ADDI:%[0-9]+]]:gprnox0 = ADDI $x0, -2
    ; CHECK-NEXT: [[PseudoVMCLR_M_B1_:%[0-9]+]]:vr = PseudoVMCLR_M_B1 [[ADDI]], 0 /* e8 */
    ; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B1_]]
    ; CHECK-NEXT: PseudoRET implicit $v0
    %0:gprb(s64) = G_CONSTANT i64 -2
    %1:vrb(<vscale x 1 x s1>) = G_VMCLR_VL %0(s64)
    $v0 = COPY %1(<vscale x 1 x s1>)
    PseudoRET implicit $v0
...
---
name:            nonconst_vl
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.1:
    liveins: $x10
    ; CHECK-LABEL: name: nonconst_vl
    ; CHECK: liveins: $x10
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprnox0 = COPY $x10
    ; CHECK-NEXT: [[PseudoVMCLR_M_B1_:%[0-9]+]]:vr = PseudoVMCLR_M_B1 [[COPY]], 0 /* e8 */
    ; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B1_]]
    ; CHECK-NEXT: PseudoRET implicit $v0
    %0:gprb(s64) = COPY $x10
    %1:vrb(<vscale x 1 x s1>) = G_VMCLR_VL %0(s64)
    $v0 = COPY %1(<vscale x 1 x s1>)
    PseudoRET implicit $v0
...

---
name:            nonzero_vl
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.1:
    ; CHECK-LABEL: name: nonzero_vl
    ; CHECK: [[PseudoVMCLR_M_B1_:%[0-9]+]]:vr = PseudoVMCLR_M_B1 1, 0 /* e8 */
    ; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B1_]]
    ; CHECK-NEXT: PseudoRET implicit $v0
    %0:gprb(s64) = G_CONSTANT i64 1
    %1:vrb(<vscale x 1 x s1>) = G_VMCLR_VL %0(s64)
    $v0 = COPY %1(<vscale x 1 x s1>)
    PseudoRET implicit $v0
...

---
name:            zero_vl
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.1:
    ; CHECK-LABEL: name: zero_vl
    ; CHECK: [[PseudoVMCLR_M_B1_:%[0-9]+]]:vr = PseudoVMCLR_M_B1 0, 0 /* e8 */
    ; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B1_]]
    ; CHECK-NEXT: PseudoRET implicit $v0
    %0:gprb(s64) = G_CONSTANT i64 0
    %1:vrb(<vscale x 1 x s1>) = G_VMCLR_VL %0(s64)
    $v0 = COPY %1(<vscale x 1 x s1>)
    PseudoRET implicit $v0
...