llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/vmclr-rv64.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=riscv64 -mattr=+v,+m -run-pass=instruction-select \
# RUN:   -simplify-mir -verify-machineinstrs %s -o - | FileCheck %s

---
name:            splat_zero_nxv1i1
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.1:
    ; CHECK-LABEL: name: splat_zero_nxv1i1
    ; CHECK: [[PseudoVMCLR_M_B1_:%[0-9]+]]:vr = PseudoVMCLR_M_B1 -1, 0 /* e8 */
    ; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B1_]]
    ; CHECK-NEXT: PseudoRET implicit $v0
    %0:gprb(s64) = G_CONSTANT i64 -1
    %1:vrb(<vscale x 1 x s1>) = G_VMCLR_VL %0(s64)
    $v0 = COPY %1(<vscale x 1 x s1>)
    PseudoRET implicit $v0

...
---
name:            splat_zero_nxv2i1
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.1:
    ; CHECK-LABEL: name: splat_zero_nxv2i1
    ; CHECK: [[PseudoVMCLR_M_B2_:%[0-9]+]]:vr = PseudoVMCLR_M_B2 -1, 0 /* e8 */
    ; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B2_]]
    ; CHECK-NEXT: PseudoRET implicit $v0
    %0:gprb(s64) = G_CONSTANT i64 -1
    %1:vrb(<vscale x 2 x s1>) = G_VMCLR_VL %0(s64)
    $v0 = COPY %1(<vscale x 2 x s1>)
    PseudoRET implicit $v0

...
---
name:            splat_zero_nxv4i1
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.1:
    ; CHECK-LABEL: name: splat_zero_nxv4i1
    ; CHECK: [[PseudoVMCLR_M_B4_:%[0-9]+]]:vr = PseudoVMCLR_M_B4 -1, 0 /* e8 */
    ; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B4_]]
    ; CHECK-NEXT: PseudoRET implicit $v0
    %0:gprb(s64) = G_CONSTANT i64 -1
    %1:vrb(<vscale x 4 x s1>) = G_VMCLR_VL %0(s64)
    $v0 = COPY %1(<vscale x 4 x s1>)
    PseudoRET implicit $v0

...
---
name:            splat_zero_nxv8i1
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.1:
    ; CHECK-LABEL: name: splat_zero_nxv8i1
    ; CHECK: [[PseudoVMCLR_M_B8_:%[0-9]+]]:vr = PseudoVMCLR_M_B8 -1, 0 /* e8 */
    ; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B8_]]
    ; CHECK-NEXT: PseudoRET implicit $v0
    %0:gprb(s64) = G_CONSTANT i64 -1
    %1:vrb(<vscale x 8 x s1>) = G_VMCLR_VL %0(s64)
    $v0 = COPY %1(<vscale x 8 x s1>)
    PseudoRET implicit $v0

...
---
name:            splat_zero_nxv16i1
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.1:
    ; CHECK-LABEL: name: splat_zero_nxv16i1
    ; CHECK: [[PseudoVMCLR_M_B16_:%[0-9]+]]:vr = PseudoVMCLR_M_B16 -1, 0 /* e8 */
    ; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B16_]]
    ; CHECK-NEXT: PseudoRET implicit $v0
    %0:gprb(s64) = G_CONSTANT i64 -1
    %1:vrb(<vscale x 16 x s1>) = G_VMCLR_VL %0(s64)
    $v0 = COPY %1(<vscale x 16 x s1>)
    PseudoRET implicit $v0

...
---
name:            splat_zero_nxv32i1
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.1:
    ; CHECK-LABEL: name: splat_zero_nxv32i1
    ; CHECK: [[PseudoVMCLR_M_B32_:%[0-9]+]]:vr = PseudoVMCLR_M_B32 -1, 0 /* e8 */
    ; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B32_]]
    ; CHECK-NEXT: PseudoRET implicit $v0
    %0:gprb(s64) = G_CONSTANT i64 -1
    %1:vrb(<vscale x 32 x s1>) = G_VMCLR_VL %0(s64)
    $v0 = COPY %1(<vscale x 32 x s1>)
    PseudoRET implicit $v0

...
---
name:            splat_zero_nxv64i1
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.1:
    ; CHECK-LABEL: name: splat_zero_nxv64i1
    ; CHECK: [[PseudoVMCLR_M_B64_:%[0-9]+]]:vr = PseudoVMCLR_M_B64 -1, 0 /* e8 */
    ; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B64_]]
    ; CHECK-NEXT: PseudoRET implicit $v0
    %0:gprb(s64) = G_CONSTANT i64 -1
    %1:vrb(<vscale x 64 x s1>) = G_VMCLR_VL %0(s64)
    $v0 = COPY %1(<vscale x 64 x s1>)
    PseudoRET implicit $v0

...