//===-- TargetInstrInfo.cpp - Target Instruction Information --------------===// // // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// // // This file implements the TargetInstrInfo class. // //===----------------------------------------------------------------------===// #include "llvm/CodeGen/TargetInstrInfo.h" #include "llvm/ADT/StringExtras.h" #include "llvm/BinaryFormat/Dwarf.h" #include "llvm/CodeGen/MachineCombinerPattern.h" #include "llvm/CodeGen/MachineFrameInfo.h" #include "llvm/CodeGen/MachineInstrBuilder.h" #include "llvm/CodeGen/MachineMemOperand.h" #include "llvm/CodeGen/MachineRegisterInfo.h" #include "llvm/CodeGen/MachineScheduler.h" #include "llvm/CodeGen/MachineTraceMetrics.h" #include "llvm/CodeGen/PseudoSourceValue.h" #include "llvm/CodeGen/ScoreboardHazardRecognizer.h" #include "llvm/CodeGen/StackMaps.h" #include "llvm/CodeGen/TargetFrameLowering.h" #include "llvm/CodeGen/TargetLowering.h" #include "llvm/CodeGen/TargetRegisterInfo.h" #include "llvm/CodeGen/TargetSchedule.h" #include "llvm/IR/DataLayout.h" #include "llvm/IR/DebugInfoMetadata.h" #include "llvm/MC/MCAsmInfo.h" #include "llvm/MC/MCInstrItineraries.h" #include "llvm/Support/CommandLine.h" #include "llvm/Support/ErrorHandling.h" #include "llvm/Support/raw_ostream.h" #include "llvm/Target/TargetMachine.h" usingnamespacellvm; static cl::opt<bool> DisableHazardRecognizer( "disable-sched-hazard", cl::Hidden, cl::init(false), cl::desc("Disable hazard detection during preRA scheduling")); TargetInstrInfo::~TargetInstrInfo() = default; const TargetRegisterClass* TargetInstrInfo::getRegClass(const MCInstrDesc &MCID, unsigned OpNum, const TargetRegisterInfo *TRI, const MachineFunction &MF) const { … } /// insertNoop - Insert a noop into the instruction stream at the specified /// point. void TargetInstrInfo::insertNoop(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const { … } /// insertNoops - Insert noops into the instruction stream at the specified /// point. void TargetInstrInfo::insertNoops(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned Quantity) const { … } static bool isAsmComment(const char *Str, const MCAsmInfo &MAI) { … } /// Measure the specified inline asm to determine an approximation of its /// length. /// Comments (which run till the next SeparatorString or newline) do not /// count as an instruction. /// Any other non-whitespace text is considered an instruction, with /// multiple instructions separated by SeparatorString or newlines. /// Variable-length instructions are not handled here; this function /// may be overloaded in the target code to do that. /// We implement a special case of the .space directive which takes only a /// single integer argument in base 10 that is the size in bytes. This is a /// restricted form of the GAS directive in that we only interpret /// simple--i.e. not a logical or arithmetic expression--size values without /// the optional fill value. This is primarily used for creating arbitrary /// sized inline asm blocks for testing purposes. unsigned TargetInstrInfo::getInlineAsmLength( const char *Str, const MCAsmInfo &MAI, const TargetSubtargetInfo *STI) const { … } /// ReplaceTailWithBranchTo - Delete the instruction OldInst and everything /// after it, replacing it with an unconditional branch to NewDest. void TargetInstrInfo::ReplaceTailWithBranchTo(MachineBasicBlock::iterator Tail, MachineBasicBlock *NewDest) const { … } MachineInstr *TargetInstrInfo::commuteInstructionImpl(MachineInstr &MI, bool NewMI, unsigned Idx1, unsigned Idx2) const { … } MachineInstr *TargetInstrInfo::commuteInstruction(MachineInstr &MI, bool NewMI, unsigned OpIdx1, unsigned OpIdx2) const { … } bool TargetInstrInfo::fixCommutedOpIndices(unsigned &ResultIdx1, unsigned &ResultIdx2, unsigned CommutableOpIdx1, unsigned CommutableOpIdx2) { … } bool TargetInstrInfo::findCommutedOpIndices(const MachineInstr &MI, unsigned &SrcOpIdx1, unsigned &SrcOpIdx2) const { … } bool TargetInstrInfo::isUnpredicatedTerminator(const MachineInstr &MI) const { … } bool TargetInstrInfo::PredicateInstruction( MachineInstr &MI, ArrayRef<MachineOperand> Pred) const { … } bool TargetInstrInfo::hasLoadFromStackSlot( const MachineInstr &MI, SmallVectorImpl<const MachineMemOperand *> &Accesses) const { … } bool TargetInstrInfo::hasStoreToStackSlot( const MachineInstr &MI, SmallVectorImpl<const MachineMemOperand *> &Accesses) const { … } bool TargetInstrInfo::getStackSlotRange(const TargetRegisterClass *RC, unsigned SubIdx, unsigned &Size, unsigned &Offset, const MachineFunction &MF) const { … } void TargetInstrInfo::reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, Register DestReg, unsigned SubIdx, const MachineInstr &Orig, const TargetRegisterInfo &TRI) const { … } bool TargetInstrInfo::produceSameValue(const MachineInstr &MI0, const MachineInstr &MI1, const MachineRegisterInfo *MRI) const { … } MachineInstr & TargetInstrInfo::duplicate(MachineBasicBlock &MBB, MachineBasicBlock::iterator InsertBefore, const MachineInstr &Orig) const { … } // If the COPY instruction in MI can be folded to a stack operation, return // the register class to use. static const TargetRegisterClass *canFoldCopy(const MachineInstr &MI, const TargetInstrInfo &TII, unsigned FoldIdx) { … } MCInst TargetInstrInfo::getNop() const { … } std::pair<unsigned, unsigned> TargetInstrInfo::getPatchpointUnfoldableRange(const MachineInstr &MI) const { … } static MachineInstr *foldPatchpoint(MachineFunction &MF, MachineInstr &MI, ArrayRef<unsigned> Ops, int FrameIndex, const TargetInstrInfo &TII) { … } static void foldInlineAsmMemOperand(MachineInstr *MI, unsigned OpNo, int FI, const TargetInstrInfo &TII) { … } // Returns nullptr if not possible to fold. static MachineInstr *foldInlineAsmMemOperand(MachineInstr &MI, ArrayRef<unsigned> Ops, int FI, const TargetInstrInfo &TII) { … } MachineInstr *TargetInstrInfo::foldMemoryOperand(MachineInstr &MI, ArrayRef<unsigned> Ops, int FI, LiveIntervals *LIS, VirtRegMap *VRM) const { … } MachineInstr *TargetInstrInfo::foldMemoryOperand(MachineInstr &MI, ArrayRef<unsigned> Ops, MachineInstr &LoadMI, LiveIntervals *LIS) const { … } /// transferImplicitOperands - MI is a pseudo-instruction, and the lowered /// replacement instructions immediately precede it. Copy any implicit /// operands from MI to the replacement instruction. static void transferImplicitOperands(MachineInstr *MI, const TargetRegisterInfo *TRI) { … } void TargetInstrInfo::lowerCopy(MachineInstr *MI, const TargetRegisterInfo *TRI) const { … } bool TargetInstrInfo::hasReassociableOperands( const MachineInstr &Inst, const MachineBasicBlock *MBB) const { … } bool TargetInstrInfo::areOpcodesEqualOrInverse(unsigned Opcode1, unsigned Opcode2) const { … } bool TargetInstrInfo::hasReassociableSibling(const MachineInstr &Inst, bool &Commuted) const { … } // 1. The operation must be associative and commutative or be the inverse of // such an operation. // 2. The instruction must have virtual register definitions for its // operands in the same basic block. // 3. The instruction must have a reassociable sibling. bool TargetInstrInfo::isReassociationCandidate(const MachineInstr &Inst, bool &Commuted) const { … } // The concept of the reassociation pass is that these operations can benefit // from this kind of transformation: // // A = ? op ? // B = A op X (Prev) // C = B op Y (Root) // --> // A = ? op ? // B = X op Y // C = A op B // // breaking the dependency between A and B, allowing them to be executed in // parallel (or back-to-back in a pipeline) instead of depending on each other. // FIXME: This has the potential to be expensive (compile time) while not // improving the code at all. Some ways to limit the overhead: // 1. Track successful transforms; bail out if hit rate gets too low. // 2. Only enable at -O3 or some other non-default optimization level. // 3. Pre-screen pattern candidates here: if an operand of the previous // instruction is known to not increase the critical path, then don't match // that pattern. bool TargetInstrInfo::getMachineCombinerPatterns( MachineInstr &Root, SmallVectorImpl<unsigned> &Patterns, bool DoRegPressureReduce) const { … } /// Return true when a code sequence can improve loop throughput. bool TargetInstrInfo::isThroughputPattern(unsigned Pattern) const { … } CombinerObjective TargetInstrInfo::getCombinerObjective(unsigned Pattern) const { … } std::pair<unsigned, unsigned> TargetInstrInfo::getReassociationOpcodes(unsigned Pattern, const MachineInstr &Root, const MachineInstr &Prev) const { … } // Return a pair of boolean flags showing if the new root and new prev operands // must be swapped. See visual example of the rule in // TargetInstrInfo::getReassociationOpcodes. static std::pair<bool, bool> mustSwapOperands(unsigned Pattern) { … } void TargetInstrInfo::getReassociateOperandIndices( const MachineInstr &Root, unsigned Pattern, std::array<unsigned, 5> &OperandIndices) const { … } /// Attempt the reassociation transformation to reduce critical path length. /// See the above comments before getMachineCombinerPatterns(). void TargetInstrInfo::reassociateOps( MachineInstr &Root, MachineInstr &Prev, unsigned Pattern, SmallVectorImpl<MachineInstr *> &InsInstrs, SmallVectorImpl<MachineInstr *> &DelInstrs, ArrayRef<unsigned> OperandIndices, DenseMap<unsigned, unsigned> &InstrIdxForVirtReg) const { … } void TargetInstrInfo::genAlternativeCodeSequence( MachineInstr &Root, unsigned Pattern, SmallVectorImpl<MachineInstr *> &InsInstrs, SmallVectorImpl<MachineInstr *> &DelInstrs, DenseMap<unsigned, unsigned> &InstIdxForVirtReg) const { … } MachineTraceStrategy TargetInstrInfo::getMachineCombinerTraceStrategy() const { … } bool TargetInstrInfo::isReallyTriviallyReMaterializable( const MachineInstr &MI) const { … } int TargetInstrInfo::getSPAdjust(const MachineInstr &MI) const { … } /// isSchedulingBoundary - Test if the given instruction should be /// considered a scheduling boundary. This primarily includes labels /// and terminators. bool TargetInstrInfo::isSchedulingBoundary(const MachineInstr &MI, const MachineBasicBlock *MBB, const MachineFunction &MF) const { … } // Provide a global flag for disabling the PreRA hazard recognizer that targets // may choose to honor. bool TargetInstrInfo::usePreRAHazardRecognizer() const { … } // Default implementation of CreateTargetRAHazardRecognizer. ScheduleHazardRecognizer *TargetInstrInfo:: CreateTargetHazardRecognizer(const TargetSubtargetInfo *STI, const ScheduleDAG *DAG) const { … } // Default implementation of CreateTargetMIHazardRecognizer. ScheduleHazardRecognizer *TargetInstrInfo::CreateTargetMIHazardRecognizer( const InstrItineraryData *II, const ScheduleDAGMI *DAG) const { … } // Default implementation of CreateTargetPostRAHazardRecognizer. ScheduleHazardRecognizer *TargetInstrInfo:: CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II, const ScheduleDAG *DAG) const { … } // Default implementation of getMemOperandWithOffset. bool TargetInstrInfo::getMemOperandWithOffset( const MachineInstr &MI, const MachineOperand *&BaseOp, int64_t &Offset, bool &OffsetIsScalable, const TargetRegisterInfo *TRI) const { … } //===----------------------------------------------------------------------===// // SelectionDAG latency interface. //===----------------------------------------------------------------------===// std::optional<unsigned> TargetInstrInfo::getOperandLatency(const InstrItineraryData *ItinData, SDNode *DefNode, unsigned DefIdx, SDNode *UseNode, unsigned UseIdx) const { … } unsigned TargetInstrInfo::getInstrLatency(const InstrItineraryData *ItinData, SDNode *N) const { … } //===----------------------------------------------------------------------===// // MachineInstr latency interface. //===----------------------------------------------------------------------===// unsigned TargetInstrInfo::getNumMicroOps(const InstrItineraryData *ItinData, const MachineInstr &MI) const { … } /// Return the default expected latency for a def based on it's opcode. unsigned TargetInstrInfo::defaultDefLatency(const MCSchedModel &SchedModel, const MachineInstr &DefMI) const { … } unsigned TargetInstrInfo::getPredicationCost(const MachineInstr &) const { … } unsigned TargetInstrInfo::getInstrLatency(const InstrItineraryData *ItinData, const MachineInstr &MI, unsigned *PredCost) const { … } bool TargetInstrInfo::hasLowDefLatency(const TargetSchedModel &SchedModel, const MachineInstr &DefMI, unsigned DefIdx) const { … } bool TargetInstrInfo::isFunctionSafeToSplit(const MachineFunction &MF) const { … } std::optional<ParamLoadedValue> TargetInstrInfo::describeLoadedValue(const MachineInstr &MI, Register Reg) const { … } // Get the call frame size just before MI. unsigned TargetInstrInfo::getCallFrameSizeAt(MachineInstr &MI) const { … } /// Both DefMI and UseMI must be valid. By default, call directly to the /// itinerary. This may be overriden by the target. std::optional<unsigned> TargetInstrInfo::getOperandLatency( const InstrItineraryData *ItinData, const MachineInstr &DefMI, unsigned DefIdx, const MachineInstr &UseMI, unsigned UseIdx) const { … } bool TargetInstrInfo::getRegSequenceInputs( const MachineInstr &MI, unsigned DefIdx, SmallVectorImpl<RegSubRegPairAndIdx> &InputRegs) const { … } bool TargetInstrInfo::getExtractSubregInputs( const MachineInstr &MI, unsigned DefIdx, RegSubRegPairAndIdx &InputReg) const { … } bool TargetInstrInfo::getInsertSubregInputs( const MachineInstr &MI, unsigned DefIdx, RegSubRegPair &BaseReg, RegSubRegPairAndIdx &InsertedReg) const { … } // Returns a MIRPrinter comment for this machine operand. std::string TargetInstrInfo::createMIROperandComment( const MachineInstr &MI, const MachineOperand &Op, unsigned OpIdx, const TargetRegisterInfo *TRI) const { … } TargetInstrInfo::PipelinerLoopInfo::~PipelinerLoopInfo() = default; void TargetInstrInfo::mergeOutliningCandidateAttributes( Function &F, std::vector<outliner::Candidate> &Candidates) const { … } outliner::InstrType TargetInstrInfo::getOutliningType(const MachineModuleInfo &MMI, MachineBasicBlock::iterator &MIT, unsigned Flags) const { … } bool TargetInstrInfo::isMBBSafeToOutlineFrom(MachineBasicBlock &MBB, unsigned &Flags) const { … }
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