/* SPDX-License-Identifier: GPL-2.0 * * Copyright 2016-2020 HabanaLabs, Ltd. * All Rights Reserved. * */ /************************************ ** This is an auto-generated file ** ** DO NOT EDIT BELOW ** ************************************/ #ifndef ASIC_REG_PSOC_GLOBAL_CONF_REGS_H_ #define ASIC_REG_PSOC_GLOBAL_CONF_REGS_H_ /* ***************************************** * PSOC_GLOBAL_CONF * (Prototype: GLOBAL_CONF) ***************************************** */ #define mmPSOC_GLOBAL_CONF_NON_RST_FLOPS_0 … #define mmPSOC_GLOBAL_CONF_NON_RST_FLOPS_1 … #define mmPSOC_GLOBAL_CONF_NON_RST_FLOPS_2 … #define mmPSOC_GLOBAL_CONF_NON_RST_FLOPS_3 … #define mmPSOC_GLOBAL_CONF_PCI_FW_FSM … #define mmPSOC_GLOBAL_CONF_BOOT_SEQ_RE_START … #define mmPSOC_GLOBAL_CONF_BTM_FSM … #define mmPSOC_GLOBAL_CONF_BTL_ROM_DELAY … #define mmPSOC_GLOBAL_CONF_SW_BTM_FSM … #define mmPSOC_GLOBAL_CONF_SW_BOOT_SEQ_FSM … #define mmPSOC_GLOBAL_CONF_BOOT_SEQ_TIMEOUT … #define mmPSOC_GLOBAL_CONF_QSPI_SPI … #define mmPSOC_GLOBAL_CONF_SPI_MEM_EN … #define mmPSOC_GLOBAL_CONF_PRSTN … #define mmPSOC_GLOBAL_CONF_PCIE_EN … #define mmPSOC_GLOBAL_CONF_PCIE_PRSTN_INTR … #define mmPSOC_GLOBAL_CONF_SPI_IMG_STS … #define mmPSOC_GLOBAL_CONF_BOOT_SEQ_FSM … #define mmPSOC_GLOBAL_CONF_BOOT_SEQ_EXT_LD … #define mmPSOC_GLOBAL_CONF_QSPI_SPI_BOOTSEQ_RST … #define mmPSOC_GLOBAL_CONF_PHY_STABLE … #define mmPSOC_GLOBAL_CONF_PRSTN_OVR … #define mmPSOC_GLOBAL_CONF_ETR_FLUSH … #define mmPSOC_GLOBAL_CONF_ANY_RST … #define mmPSOC_GLOBAL_CONF_COLD_RST_FLOPS_0 … #define mmPSOC_GLOBAL_CONF_COLD_RST_FLOPS_1 … #define mmPSOC_GLOBAL_CONF_COLD_RST_FLOPS_2 … #define mmPSOC_GLOBAL_CONF_COLD_RST_FLOPS_3 … #define mmPSOC_GLOBAL_CONF_DIS_RAZWI_ERR … #define mmPSOC_GLOBAL_CONF_PCIE_PHY_RST_N … #define mmPSOC_GLOBAL_CONF_RAZWI_INTERRUPT … #define mmPSOC_GLOBAL_CONF_RAZWI_MASK_INFO … #define mmPSOC_GLOBAL_CONF_BTL_PROT … #define mmPSOC_GLOBAL_CONF_BTL_ADDR_EXT … #define mmPSOC_GLOBAL_CONF_BOOT_SEQ_TO … #define mmPSOC_GLOBAL_CONF_RESET_DELAYS … #define mmPSOC_GLOBAL_CONF_SCRATCHPAD_0 … #define mmPSOC_GLOBAL_CONF_SCRATCHPAD_1 … #define mmPSOC_GLOBAL_CONF_SCRATCHPAD_2 … #define mmPSOC_GLOBAL_CONF_SCRATCHPAD_3 … #define mmPSOC_GLOBAL_CONF_SCRATCHPAD_4 … #define mmPSOC_GLOBAL_CONF_SCRATCHPAD_5 … #define mmPSOC_GLOBAL_CONF_SCRATCHPAD_6 … #define mmPSOC_GLOBAL_CONF_SCRATCHPAD_7 … #define mmPSOC_GLOBAL_CONF_SCRATCHPAD_8 … #define mmPSOC_GLOBAL_CONF_SCRATCHPAD_9 … #define mmPSOC_GLOBAL_CONF_SCRATCHPAD_10 … #define mmPSOC_GLOBAL_CONF_SCRATCHPAD_11 … #define mmPSOC_GLOBAL_CONF_SCRATCHPAD_12 … #define mmPSOC_GLOBAL_CONF_SCRATCHPAD_13 … #define mmPSOC_GLOBAL_CONF_SCRATCHPAD_14 … #define mmPSOC_GLOBAL_CONF_SCRATCHPAD_15 … #define mmPSOC_GLOBAL_CONF_SCRATCHPAD_16 … #define mmPSOC_GLOBAL_CONF_SCRATCHPAD_17 … #define mmPSOC_GLOBAL_CONF_SCRATCHPAD_18 … #define mmPSOC_GLOBAL_CONF_SCRATCHPAD_19 … #define mmPSOC_GLOBAL_CONF_SCRATCHPAD_20 … #define mmPSOC_GLOBAL_CONF_SCRATCHPAD_21 … #define mmPSOC_GLOBAL_CONF_SCRATCHPAD_22 … #define mmPSOC_GLOBAL_CONF_SCRATCHPAD_23 … #define mmPSOC_GLOBAL_CONF_SCRATCHPAD_24 … #define mmPSOC_GLOBAL_CONF_SCRATCHPAD_25 … #define mmPSOC_GLOBAL_CONF_SCRATCHPAD_26 … #define mmPSOC_GLOBAL_CONF_SCRATCHPAD_27 … #define mmPSOC_GLOBAL_CONF_SCRATCHPAD_28 … #define mmPSOC_GLOBAL_CONF_SCRATCHPAD_29 … #define mmPSOC_GLOBAL_CONF_SCRATCHPAD_30 … #define mmPSOC_GLOBAL_CONF_SCRATCHPAD_31 … #define mmPSOC_GLOBAL_CONF_SEMAPHORE_0 … #define mmPSOC_GLOBAL_CONF_SEMAPHORE_1 … #define mmPSOC_GLOBAL_CONF_SEMAPHORE_2 … #define mmPSOC_GLOBAL_CONF_SEMAPHORE_3 … #define mmPSOC_GLOBAL_CONF_SEMAPHORE_4 … #define mmPSOC_GLOBAL_CONF_SEMAPHORE_5 … #define mmPSOC_GLOBAL_CONF_SEMAPHORE_6 … #define mmPSOC_GLOBAL_CONF_SEMAPHORE_7 … #define mmPSOC_GLOBAL_CONF_SEMAPHORE_8 … #define mmPSOC_GLOBAL_CONF_SEMAPHORE_9 … #define mmPSOC_GLOBAL_CONF_SEMAPHORE_10 … #define mmPSOC_GLOBAL_CONF_SEMAPHORE_11 … #define mmPSOC_GLOBAL_CONF_SEMAPHORE_12 … #define mmPSOC_GLOBAL_CONF_SEMAPHORE_13 … #define mmPSOC_GLOBAL_CONF_SEMAPHORE_14 … #define mmPSOC_GLOBAL_CONF_SEMAPHORE_15 … #define mmPSOC_GLOBAL_CONF_SEMAPHORE_16 … #define mmPSOC_GLOBAL_CONF_SEMAPHORE_17 … #define mmPSOC_GLOBAL_CONF_SEMAPHORE_18 … #define mmPSOC_GLOBAL_CONF_SEMAPHORE_19 … #define mmPSOC_GLOBAL_CONF_SEMAPHORE_20 … #define mmPSOC_GLOBAL_CONF_SEMAPHORE_21 … #define mmPSOC_GLOBAL_CONF_SEMAPHORE_22 … #define mmPSOC_GLOBAL_CONF_SEMAPHORE_23 … #define mmPSOC_GLOBAL_CONF_SEMAPHORE_24 … #define mmPSOC_GLOBAL_CONF_SEMAPHORE_25 … #define mmPSOC_GLOBAL_CONF_SEMAPHORE_26 … #define mmPSOC_GLOBAL_CONF_SEMAPHORE_27 … #define mmPSOC_GLOBAL_CONF_SEMAPHORE_28 … #define mmPSOC_GLOBAL_CONF_SEMAPHORE_29 … #define mmPSOC_GLOBAL_CONF_SEMAPHORE_30 … #define mmPSOC_GLOBAL_CONF_SEMAPHORE_31 … #define mmPSOC_GLOBAL_CONF_CPU_BOOT_STATUS … #define mmPSOC_GLOBAL_CONF_KMD_MSG_TO_CPU … #define mmPSOC_GLOBAL_CONF_SPL_SOURCE … #define mmPSOC_GLOBAL_CONF_I2C_MSTR1_DBG … #define mmPSOC_GLOBAL_CONF_I2C_SLV … #define mmPSOC_GLOBAL_CONF_I2C_SLV_INTR_MASK … #define mmPSOC_GLOBAL_CONF_TRACE_ADDR … #define mmPSOC_GLOBAL_CONF_SMB_ALERT_CTRL … #define mmPSOC_GLOBAL_CONF_SMB_ALERT_INTR_CAUSE … #define mmPSOC_GLOBAL_CONF_PCIE_PSOC_DERR_INTR_CLEAR … #define mmPSOC_GLOBAL_CONF_PCIE_PSOC_DERR_INTR_CTRL … #define mmPSOC_GLOBAL_CONF_TRACE_AXPROT … #define mmPSOC_GLOBAL_CONF_TRACE_AWUSER … #define mmPSOC_GLOBAL_CONF_TRACE_ARUSER … #define mmPSOC_GLOBAL_CONF_BTL_STS … #define mmPSOC_GLOBAL_CONF_TIMEOUT_INTR … #define mmPSOC_GLOBAL_CONF_COMB_TIMEOUT_INTR … #define mmPSOC_GLOBAL_CONF_PERIPH_INTR … #define mmPSOC_GLOBAL_CONF_COMB_PERIPH_INTR … #define mmPSOC_GLOBAL_CONF_AXI_ERR_INTR … #define mmPSOC_GLOBAL_CONF_ARC_WD_INTR … #define mmPSOC_GLOBAL_CONF_ARC_WD_INTR_MASK … #define mmPSOC_GLOBAL_CONF_DBG_APB_CTRL … #define mmPSOC_GLOBAL_CONF_SPI_DMA_BAUDR … #define mmPSOC_GLOBAL_CONF_SPI_DMA_AWPROT … #define mmPSOC_GLOBAL_CONF_SPI_DMA_AWUSER … #define mmPSOC_GLOBAL_CONF_SPI_DMA_CTRL … #define mmPSOC_GLOBAL_CONF_SPI_DMA_STATUS … #define mmPSOC_GLOBAL_CONF_SPI_DMA_DST_ADDR_L … #define mmPSOC_GLOBAL_CONF_SPI_DMA_DST_ADDR_H … #define mmPSOC_GLOBAL_CONF_SPI_DIRECT_WR_RD_CTRL … #define mmPSOC_GLOBAL_CONF_SPI_WR_WO_CTRL … #define mmPSOC_GLOBAL_CONF_SPI_WR_WO_TIMER_RST_VAL_L … #define mmPSOC_GLOBAL_CONF_SPI_WR_WO_TIMER_RST_VAL_H … #define mmPSOC_GLOBAL_CONF_SPI_WR_WO_TIMER_VAL_L … #define mmPSOC_GLOBAL_CONF_SPI_WR_WO_TIMER_VAL_H … #define mmPSOC_GLOBAL_CONF_QSPI_WR_WO_TIMER_VAL_L … #define mmPSOC_GLOBAL_CONF_QSPI_WR_WO_TIMER_VAL_H … #define mmPSOC_GLOBAL_CONF_SPI_WR_WO_SE_STATUS … #define mmPSOC_GLOBAL_CONF_QSPI_WR_WO_SE_STATUS … #define mmPSOC_GLOBAL_CONF_SPI_WR_WO_ERR_ADDR … #define mmPSOC_GLOBAL_CONF_QSPI_WR_WO_ERR_ADDR … #define mmPSOC_GLOBAL_CONF_SPI_WR_WO_INTR_MASK … #define mmPSOC_GLOBAL_CONF_SPI_WR_WO_INTR_CAUSE … #define mmPSOC_GLOBAL_CONF_SPI_WR_WO_INTR_CLEAR … #define mmPSOC_GLOBAL_CONF_MSTR_IF … #define mmPSOC_GLOBAL_CONF_TARGETID … #define mmPSOC_GLOBAL_CONF_ARC_LBU_AXI_SPLIT_CTRL_0 … #define mmPSOC_GLOBAL_CONF_ARC_LBU_AXI_SPLIT_CTRL_1 … #define mmPSOC_GLOBAL_CONF_ARC_LBU_AXI_SPLIT_CTRL2_0 … #define mmPSOC_GLOBAL_CONF_ARC_LBU_AXI_SPLIT_CTRL2_1 … #define mmPSOC_GLOBAL_CONF_EMMC_INT_VOL_STABLE … #define mmPSOC_GLOBAL_CONF_BOOT_STRAP_PINS_L … #define mmPSOC_GLOBAL_CONF_BOOT_STRAP_PINS_H … #define mmPSOC_GLOBAL_CONF_LEGACY_BOOT_STRAPS … #define mmPSOC_GLOBAL_CONF_MEM_REPAIR_DIV … #define mmPSOC_GLOBAL_CONF_MEM_REPAIR_CTRL … #define mmPSOC_GLOBAL_CONF_MEM_REPAIR_STS … #define mmPSOC_GLOBAL_CONF_OUTSTANT_TRANS … #define mmPSOC_GLOBAL_CONF_MASK_REQ … #define mmPSOC_GLOBAL_CONF_BSAC_CTRL … #define mmPSOC_GLOBAL_CONF_BSAC_ADDR … #define mmPSOC_GLOBAL_CONF_BSAC_DATA … #define mmPSOC_GLOBAL_CONF_BSAC_POLLING_CTRL … #define mmPSOC_GLOBAL_CONF_BSAC_POLLING_DATA … #define mmPSOC_GLOBAL_CONF_BSAC_POLLING_MASK … #define mmPSOC_GLOBAL_CONF_BTL_IMG … #define mmPSOC_GLOBAL_CONF_PRSTN_MASK … #define mmPSOC_GLOBAL_CONF_WD_MASK … #define mmPSOC_GLOBAL_CONF_RST_SRC … #define mmPSOC_GLOBAL_CONF_BOOT_STATE … #define mmPSOC_GLOBAL_CONF_RST_FROM_PCIE_CTRL … #define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_0 … #define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_1 … #define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_2 … #define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_3 … #define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_4 … #define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_5 … #define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_6 … #define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_7 … #define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_8 … #define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_9 … #define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_10 … #define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_11 … #define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_12 … #define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_13 … #define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_14 … #define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_15 … #define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_16 … #define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_17 … #define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_18 … #define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_19 … #define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_20 … #define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_21 … #define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_22 … #define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_23 … #define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_24 … #define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_25 … #define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_26 … #define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_27 … #define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_28 … #define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_29 … #define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_30 … #define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_31 … #define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_32 … #define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_33 … #define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_34 … #define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_35 … #define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_36 … #define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_37 … #define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_38 … #define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_39 … #define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_40 … #define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_41 … #define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_42 … #define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_43 … #define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_44 … #define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_45 … #define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_46 … #define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_47 … #define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_48 … #define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_49 … #define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_50 … #define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_51 … #define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_52 … #define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_53 … #define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_54 … #define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_55 … #define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_56 … #define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_57 … #define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_58 … #define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_59 … #define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_60 … #define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_61 … #define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_62 … #define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_63 … #define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_64 … #define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_65 … #define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_66 … #define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_67 … #define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_68 … #define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_69 … #define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_70 … #define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_71 … #define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_72 … #define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_73 … #define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_74 … #define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_75 … #define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_76 … #define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_77 … #define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_78 … #define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_79 … #define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_80 … #define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_81 … #define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_82 … #define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_83 … #define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_84 … #define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_85 … #define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_86 … #define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_87 … #define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_88 … #define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_89 … #define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_90 … #define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_91 … #define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_92 … #define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_93 … #define mmPSOC_GLOBAL_CONF_PAD_3V3_CFG_0 … #define mmPSOC_GLOBAL_CONF_PAD_3V3_CFG_1 … #define mmPSOC_GLOBAL_CONF_PAD_3V3_CFG_2 … #define mmPSOC_GLOBAL_CONF_PAD_3V3_CFG_3 … #define mmPSOC_GLOBAL_CONF_PAD_3V3_CFG_4 … #define mmPSOC_GLOBAL_CONF_PAD_3V3_CFG_5 … #define mmPSOC_GLOBAL_CONF_PAD_3V3_CFG_6 … #define mmPSOC_GLOBAL_CONF_PAD_3V3_CFG_7 … #define mmPSOC_GLOBAL_CONF_PAD_3V3_CFG_8 … #define mmPSOC_GLOBAL_CONF_PAD_3V3_CFG_9 … #define mmPSOC_GLOBAL_CONF_PAD_3V3_CFG_10 … #define mmPSOC_GLOBAL_CONF_PAD_3V3_CFG_11 … #define mmPSOC_GLOBAL_CONF_BNK3V3_MS … #define mmPSOC_GLOBAL_CONF_TPC_ISO … #define mmPSOC_GLOBAL_CONF_VDEC_ISO … #define mmPSOC_GLOBAL_CONF_NIC_ISO … #define mmPSOC_GLOBAL_CONF_MME_ISO … #define mmPSOC_GLOBAL_CONF_EDMA_ISO … #define mmPSOC_GLOBAL_CONF_HBM_ISO … #define mmPSOC_GLOBAL_CONF_XBAR_EDGE_ISO … #define mmPSOC_GLOBAL_CONF_HIF_HMMU_ISO … #define mmPSOC_GLOBAL_CONF_ASIF_MSTR_REQ_STATUS_0 … #define mmPSOC_GLOBAL_CONF_ASIF_MSTR_REQ_STATUS_1 … #define mmPSOC_GLOBAL_CONF_ASIF_MSTR_REQ_PUSH_0 … #define mmPSOC_GLOBAL_CONF_ASIF_MSTR_REQ_PUSH_1 … #define mmPSOC_GLOBAL_CONF_ASIF_MSTR_REQ_WR_0 … #define mmPSOC_GLOBAL_CONF_ASIF_MSTR_REQ_WR_1 … #define mmPSOC_GLOBAL_CONF_ASIF_MSTR_RES_STATUS_0 … #define mmPSOC_GLOBAL_CONF_ASIF_MSTR_RES_STATUS_1 … #define mmPSOC_GLOBAL_CONF_ASIF_MSTR_RES_POP_0 … #define mmPSOC_GLOBAL_CONF_ASIF_MSTR_RES_POP_1 … #define mmPSOC_GLOBAL_CONF_ASIF_MSTR_ERROR_0 … #define mmPSOC_GLOBAL_CONF_ASIF_MSTR_ERROR_1 … #define mmPSOC_GLOBAL_CONF_ASIF_MSTR_INTR_MASK_0 … #define mmPSOC_GLOBAL_CONF_ASIF_MSTR_INTR_MASK_1 … #define mmPSOC_GLOBAL_CONF_ASIF_MSTR_STATUS … #define mmPSOC_GLOBAL_CONF_ASIF_CORE_CFG … #define mmPSOC_GLOBAL_CONF_ASIF_CORE_DBG_CNT … #define mmPSOC_GLOBAL_CONF_ASIF_CORE_DBG_CNT_CLR … #define mmPSOC_GLOBAL_CONF_ASIF_CORE_TIMEOUT_CFG … #define mmPSOC_GLOBAL_CONF_ASIF_FUNC_INTR_CAUSE_0 … #define mmPSOC_GLOBAL_CONF_ASIF_FUNC_INTR_CAUSE_1 … #define mmPSOC_GLOBAL_CONF_ASIF_FUNC_INTR_CLEAR_0 … #define mmPSOC_GLOBAL_CONF_ASIF_FUNC_INTR_CLEAR_1 … #define mmPSOC_GLOBAL_CONF_ASIF_FUNC_INTR_MASK_0 … #define mmPSOC_GLOBAL_CONF_ASIF_FUNC_INTR_MASK_1 … #define mmPSOC_GLOBAL_CONF_ASIF_ERR_INTR_CAUSE_0 … #define mmPSOC_GLOBAL_CONF_ASIF_ERR_INTR_CAUSE_1 … #define mmPSOC_GLOBAL_CONF_ASIF_ERR_INTR_CLEAR_0 … #define mmPSOC_GLOBAL_CONF_ASIF_ERR_INTR_CLEAR_1 … #define mmPSOC_GLOBAL_CONF_ASIF_ERR_INTR_MASK_0 … #define mmPSOC_GLOBAL_CONF_ASIF_ERR_INTR_MASK_1 … #define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_0 … #define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_1 … #define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_2 … #define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_3 … #define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_4 … #define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_5 … #define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_6 … #define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_7 … #define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_8 … #define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_9 … #define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_10 … #define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_11 … #define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_12 … #define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_13 … #define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_14 … #define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_15 … #define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_16 … #define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_17 … #define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_18 … #define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_19 … #define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_20 … #define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_21 … #define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_22 … #define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_23 … #define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_24 … #define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_25 … #define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_26 … #define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_27 … #define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_28 … #define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_29 … #define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_30 … #define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_31 … #define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_32 … #define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_33 … #define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_34 … #define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_35 … #define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_36 … #define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_37 … #define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_38 … #define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_39 … #define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_40 … #define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_41 … #define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_42 … #define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_43 … #define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_44 … #define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_45 … #define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_46 … #define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_47 … #define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_48 … #define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_49 … #define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_50 … #define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_51 … #define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_52 … #define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_53 … #define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_54 … #define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_55 … #define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_56 … #define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_57 … #define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_58 … #define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_59 … #define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_60 … #define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_61 … #define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_62 … #define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_63 … #define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_64 … #define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_65 … #define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_66 … #define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_67 … #define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_68 … #define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_69 … #define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_70 … #define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_71 … #define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_72 … #define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_73 … #define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_74 … #define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_75 … #define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_76 … #define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_77 … #define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_78 … #define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_79 … #define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_80 … #define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_81 … #define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_82 … #define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_83 … #define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_84 … #define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_85 … #define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_86 … #define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_87 … #define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_88 … #define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_89 … #define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_90 … #define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_91 … #define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_92 … #define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_93 … #define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_94 … #define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_95 … #define mmPSOC_GLOBAL_CONF_PAD_SEL_0 … #define mmPSOC_GLOBAL_CONF_PAD_SEL_1 … #define mmPSOC_GLOBAL_CONF_PAD_SEL_2 … #define mmPSOC_GLOBAL_CONF_PAD_SEL_3 … #define mmPSOC_GLOBAL_CONF_PAD_SEL_4 … #define mmPSOC_GLOBAL_CONF_PAD_SEL_5 … #define mmPSOC_GLOBAL_CONF_PAD_SEL_6 … #define mmPSOC_GLOBAL_CONF_PAD_SEL_7 … #define mmPSOC_GLOBAL_CONF_PAD_SEL_8 … #define mmPSOC_GLOBAL_CONF_PAD_SEL_9 … #define mmPSOC_GLOBAL_CONF_PAD_SEL_10 … #define mmPSOC_GLOBAL_CONF_PAD_SEL_11 … #define mmPSOC_GLOBAL_CONF_PAD_SEL_12 … #define mmPSOC_GLOBAL_CONF_PAD_SEL_13 … #define mmPSOC_GLOBAL_CONF_PAD_SEL_14 … #define mmPSOC_GLOBAL_CONF_PAD_SEL_15 … #define mmPSOC_GLOBAL_CONF_PAD_SEL_16 … #define mmPSOC_GLOBAL_CONF_PAD_SEL_17 … #define mmPSOC_GLOBAL_CONF_PAD_SEL_18 … #define mmPSOC_GLOBAL_CONF_PAD_SEL_19 … #define mmPSOC_GLOBAL_CONF_PAD_SEL_20 … #define mmPSOC_GLOBAL_CONF_PAD_SEL_21 … #define mmPSOC_GLOBAL_CONF_PAD_SEL_22 … #define mmPSOC_GLOBAL_CONF_PAD_SEL_23 … #define mmPSOC_GLOBAL_CONF_PAD_SEL_24 … #define mmPSOC_GLOBAL_CONF_PAD_SEL_25 … #define mmPSOC_GLOBAL_CONF_PAD_SEL_26 … #define mmPSOC_GLOBAL_CONF_PAD_SEL_27 … #define mmPSOC_GLOBAL_CONF_PAD_SEL_28 … #define mmPSOC_GLOBAL_CONF_PAD_SEL_29 … #define mmPSOC_GLOBAL_CONF_PAD_SEL_30 … #define mmPSOC_GLOBAL_CONF_PAD_SEL_31 … #define mmPSOC_GLOBAL_CONF_PAD_SEL_32 … #define mmPSOC_GLOBAL_CONF_PAD_SEL_33 … #define mmPSOC_GLOBAL_CONF_PAD_SEL_34 … #define mmPSOC_GLOBAL_CONF_PAD_SEL_35 … #define mmPSOC_GLOBAL_CONF_PAD_SEL_36 … #define mmPSOC_GLOBAL_CONF_PAD_SEL_37 … #define mmPSOC_GLOBAL_CONF_PAD_SEL_38 … #define mmPSOC_GLOBAL_CONF_PAD_SEL_39 … #define mmPSOC_GLOBAL_CONF_PAD_SEL_40 … #define mmPSOC_GLOBAL_CONF_PAD_SEL_41 … #define mmPSOC_GLOBAL_CONF_PAD_SEL_42 … #define mmPSOC_GLOBAL_CONF_PAD_SEL_43 … #define mmPSOC_GLOBAL_CONF_PAD_SEL_44 … #define mmPSOC_GLOBAL_CONF_PAD_SEL_45 … #define mmPSOC_GLOBAL_CONF_PAD_SEL_46 … #define mmPSOC_GLOBAL_CONF_PAD_SEL_47 … #define mmPSOC_GLOBAL_CONF_PAD_SEL_48 … #define mmPSOC_GLOBAL_CONF_PAD_SEL_49 … #define mmPSOC_GLOBAL_CONF_PAD_SEL_50 … #define mmPSOC_GLOBAL_CONF_PAD_SEL_51 … #define mmPSOC_GLOBAL_CONF_PAD_SEL_52 … #define mmPSOC_GLOBAL_CONF_PAD_SEL_53 … #define mmPSOC_GLOBAL_CONF_PAD_SEL_54 … #define mmPSOC_GLOBAL_CONF_PAD_SEL_55 … #define mmPSOC_GLOBAL_CONF_PAD_SEL_56 … #define mmPSOC_GLOBAL_CONF_PAD_SEL_57 … #define mmPSOC_GLOBAL_CONF_PAD_SEL_58 … #define mmPSOC_GLOBAL_CONF_PAD_SEL_59 … #define mmPSOC_GLOBAL_CONF_PAD_SEL_60 … #define mmPSOC_GLOBAL_CONF_PAD_SEL_61 … #define mmPSOC_GLOBAL_CONF_PAD_SEL_62 … #define mmPSOC_GLOBAL_CONF_PAD_SEL_63 … #define mmPSOC_GLOBAL_CONF_PAD_SEL_64 … #define mmPSOC_GLOBAL_CONF_PAD_SEL_65 … #define mmPSOC_GLOBAL_CONF_PAD_SEL_66 … #define mmPSOC_GLOBAL_CONF_PAD_SEL_67 … #define mmPSOC_GLOBAL_CONF_PAD_SEL_68 … #define mmPSOC_GLOBAL_CONF_PAD_SEL_69 … #define mmPSOC_GLOBAL_CONF_PAD_SEL_70 … #define mmPSOC_GLOBAL_CONF_PAD_SEL_71 … #define mmPSOC_GLOBAL_CONF_PAD_SEL_72 … #define mmPSOC_GLOBAL_CONF_PAD_SEL_73 … #define mmPSOC_GLOBAL_CONF_PAD_SEL_74 … #define mmPSOC_GLOBAL_CONF_PAD_SEL_75 … #define mmPSOC_GLOBAL_CONF_PAD_SEL_76 … #define mmPSOC_GLOBAL_CONF_PAD_SEL_77 … #define mmPSOC_GLOBAL_CONF_PAD_SEL_78 … #define mmPSOC_GLOBAL_CONF_PAD_SEL_79 … #define mmPSOC_GLOBAL_CONF_PAD_SEL_80 … #define mmPSOC_GLOBAL_CONF_PAD_SEL_81 … #define mmPSOC_GLOBAL_CONF_PAD_SEL_82 … #define mmPSOC_GLOBAL_CONF_PAD_SEL_83 … #define mmPSOC_GLOBAL_CONF_PAD_SEL_84 … #define mmPSOC_GLOBAL_CONF_PAD_SEL_85 … #define mmPSOC_GLOBAL_CONF_PAD_SEL_86 … #define mmPSOC_GLOBAL_CONF_PAD_SEL_87 … #define mmPSOC_GLOBAL_CONF_PAD_SEL_88 … #define mmPSOC_GLOBAL_CONF_PAD_SEL_89 … #define mmPSOC_GLOBAL_CONF_PAD_SEL_90 … #define mmPSOC_GLOBAL_CONF_PAD_SEL_91 … #define mmPSOC_GLOBAL_CONF_PAD_SEL_92 … #define mmPSOC_GLOBAL_CONF_PAD_SEL_93 … #define mmPSOC_GLOBAL_CONF_PAD_SEL_94 … #define mmPSOC_GLOBAL_CONF_PAD_SEL_95 … #define mmPSOC_GLOBAL_CONF_SMI_ACCESS_EN … #define mmPSOC_GLOBAL_CONF_SCRAM_EXTMEM_EN … #define mmPSOC_GLOBAL_CONF_SCRAM_PERM_SEL … #define mmPSOC_GLOBAL_CONF_SCRAM_POLY_H3_0 … #define mmPSOC_GLOBAL_CONF_SCRAM_POLY_H3_1 … #define mmPSOC_GLOBAL_CONF_SCRAM_POLY_H3_2 … #define mmPSOC_GLOBAL_CONF_SCRAM_POLY_H3_3 … #define mmPSOC_GLOBAL_CONF_SCRAM_POLY_H3_4 … #define mmPSOC_GLOBAL_CONF_SCRAM_POLY_H3_5 … #define mmPSOC_GLOBAL_CONF_SCRAM_POLY_H3_6 … #define mmPSOC_GLOBAL_CONF_SCRAM_POLY_H3_7 … #define mmPSOC_GLOBAL_CONF_SCRAM_POLY_H3_8 … #define mmPSOC_GLOBAL_CONF_SCRAM_POLY_H3_9 … #define mmPSOC_GLOBAL_CONF_SCRAM_POLY_H3_10 … #define mmPSOC_GLOBAL_CONF_SCRAM_POLY_H3_11 … #define mmPSOC_GLOBAL_CONF_SCRAM_POLY_H3_12 … #define mmPSOC_GLOBAL_CONF_SCRAM_POLY_H3_13 … #define mmPSOC_GLOBAL_CONF_SCRAM_POLY_H3_14 … #define mmPSOC_GLOBAL_CONF_SCRAM_POLY_H3_15 … #define mmPSOC_GLOBAL_CONF_SCRAM_POLY_H3_16 … #define mmPSOC_GLOBAL_CONF_SCRAM_POLY_H3_17 … #define mmPSOC_GLOBAL_CONF_SCRAM_POLY_H3_18 … #define mmPSOC_GLOBAL_CONF_SCRAM_POLY_H3_19 … #define mmPSOC_GLOBAL_CONF_SCRAM_POLY_H3_20 … #define mmPSOC_GLOBAL_CONF_SCRAM_POLY_H3_21 … #define mmPSOC_GLOBAL_CONF_SCRAM_POLY_H3_22 … #define mmPSOC_GLOBAL_CONF_SCRAM_POLY_H3_23 … #define mmPSOC_GLOBAL_CONF_SCRAM_POLY_H3_24 … #define mmPSOC_GLOBAL_CONF_SCRAM_POLY_H3_25 … #define mmPSOC_GLOBAL_CONF_SCRAM_POLY_H3_26 … #define mmPSOC_GLOBAL_CONF_SCRAM_POLY_H3_27 … #define mmPSOC_GLOBAL_CONF_SCRAM_POLY_H3_28 … #define mmPSOC_GLOBAL_CONF_CORE_MODE … #define mmPSOC_GLOBAL_CONF_EXTMEM_ID_LOC … #define mmPSOC_GLOBAL_CONF_LBW_USER_CTRL … #define mmPSOC_GLOBAL_CONF_ADC_STM_ID … #define mmPSOC_GLOBAL_CONF_ADC_0 … #define mmPSOC_GLOBAL_CONF_ADC_1 … #define mmPSOC_GLOBAL_CONF_ADC_INT_MASK_0 … #define mmPSOC_GLOBAL_CONF_ADC_INT_MASK_1 … #define mmPSOC_GLOBAL_CONF_ADC_CLK_FREQ_0 … #define mmPSOC_GLOBAL_CONF_ADC_CLK_FREQ_1 … #define mmPSOC_GLOBAL_CONF_ADC_DELAY_FROM_START_0 … #define mmPSOC_GLOBAL_CONF_ADC_DELAY_FROM_START_1 … #define mmPSOC_GLOBAL_CONF_ADC_SAMPLES_0 … #define mmPSOC_GLOBAL_CONF_ADC_SAMPLES_1 … #define mmPSOC_GLOBAL_CONF_ADC_TPH_CS_0 … #define mmPSOC_GLOBAL_CONF_ADC_TPH_CS_1 … #define mmPSOC_GLOBAL_CONF_ADC_LSB_NMSB_0 … #define mmPSOC_GLOBAL_CONF_ADC_LSB_NMSB_1 … #define mmPSOC_GLOBAL_CONF_ADC_ONE_NCONTIUES_0 … #define mmPSOC_GLOBAL_CONF_ADC_ONE_NCONTIUES_1 … #define mmPSOC_GLOBAL_CONF_ADC_BLOCK_ENABLE_0 … #define mmPSOC_GLOBAL_CONF_ADC_BLOCK_ENABLE_1 … #define mmPSOC_GLOBAL_CONF_ADC_TDV_CSDO_0 … #define mmPSOC_GLOBAL_CONF_ADC_TDV_CSDO_1 … #define mmPSOC_GLOBAL_CONF_ADC_PID_SEL … #define mmPSOC_GLOBAL_CONF_ADC_TSU_CSCK_0 … #define mmPSOC_GLOBAL_CONF_ADC_TSU_CSCK_1 … #define mmPSOC_GLOBAL_CONF_ADC_CH_SEL_0 … #define mmPSOC_GLOBAL_CONF_ADC_CH_SEL_1 … #define mmPSOC_GLOBAL_CONF_ADC_WRITE_ADDR_0 … #define mmPSOC_GLOBAL_CONF_ADC_WRITE_ADDR_1 … #define mmPSOC_GLOBAL_CONF_ADC_WRITE_ADDR_2 … #define mmPSOC_GLOBAL_CONF_ADC_WRITE_ADDR_3 … #define mmPSOC_GLOBAL_CONF_ADC_WRITE_ADDR_4 … #define mmPSOC_GLOBAL_CONF_ADC_WRITE_ADDR_5 … #define mmPSOC_GLOBAL_CONF_ADC_WRITE_ADDR_6 … #define mmPSOC_GLOBAL_CONF_ADC_WRITE_ADDR_7 … #define mmPSOC_GLOBAL_CONF_ADC_CFG_DATA_0 … #define mmPSOC_GLOBAL_CONF_ADC_CFG_DATA_1 … #define mmPSOC_GLOBAL_CONF_ADC_CFG_DATA_2 … #define mmPSOC_GLOBAL_CONF_ADC_CFG_DATA_3 … #define mmPSOC_GLOBAL_CONF_ADC_CFG_DATA_4 … #define mmPSOC_GLOBAL_CONF_ADC_CFG_DATA_5 … #define mmPSOC_GLOBAL_CONF_ADC_CFG_DATA_6 … #define mmPSOC_GLOBAL_CONF_ADC_CFG_DATA_7 … #define mmPSOC_GLOBAL_CONF_ADC_AUX_STM_CTRL_0 … #define mmPSOC_GLOBAL_CONF_ADC_AUX_STM_CTRL_1 … #define mmPSOC_GLOBAL_CONF_ADC_AUX_STM_CTRL_2 … #define mmPSOC_GLOBAL_CONF_ADC_AUX_STM_CTRL_3 … #define mmPSOC_GLOBAL_CONF_ADC_AUX_STM_CTRL_4 … #define mmPSOC_GLOBAL_CONF_ADC_AUX_STM_CTRL_5 … #define mmPSOC_GLOBAL_CONF_ADC_AUX_STM_CTRL_6 … #define mmPSOC_GLOBAL_CONF_ADC_AUX_STM_CTRL_7 … #define mmPSOC_GLOBAL_CONF_TERMINATE_READ_CTRL … #define mmPSOC_GLOBAL_CONF_TERMINATE_READ_MIN_AD0_L … #define mmPSOC_GLOBAL_CONF_TERMINATE_READ_MIN_AD0_H … #define mmPSOC_GLOBAL_CONF_TERMINATE_READ_MAX_AD0_L … #define mmPSOC_GLOBAL_CONF_TERMINATE_READ_MAX_AD0_H … #define mmPSOC_GLOBAL_CONF_TERMINATE_READ_MIN_AD1_L … #define mmPSOC_GLOBAL_CONF_TERMINATE_READ_MIN_AD1_H … #define mmPSOC_GLOBAL_CONF_TERMINATE_READ_MAX_AD1_L … #define mmPSOC_GLOBAL_CONF_TERMINATE_READ_MAX_AD1_H … #define mmPSOC_GLOBAL_CONF_TERMINATE_READ_MIN_AD2_L … #define mmPSOC_GLOBAL_CONF_TERMINATE_READ_MIN_AD2_H … #define mmPSOC_GLOBAL_CONF_TERMINATE_READ_MAX_AD2_L … #define mmPSOC_GLOBAL_CONF_TERMINATE_READ_MAX_AD2_H … #define mmPSOC_GLOBAL_CONF_TERMINATE_READ_MIN_AD3_L … #define mmPSOC_GLOBAL_CONF_TERMINATE_READ_MIN_AD3_H … #define mmPSOC_GLOBAL_CONF_TERMINATE_READ_MAX_AD3_L … #define mmPSOC_GLOBAL_CONF_TERMINATE_READ_MAX_AD3_H … #define mmPSOC_GLOBAL_CONF_SCRATCHPAD_INIT_CTRL … #define mmPSOC_GLOBAL_CONF_RST_OUT_CTRL … #define mmPSOC_GLOBAL_CONF_MEM_CPY_CTRL … #define mmPSOC_GLOBAL_CONF_MEM_CPY_STATUS … #define mmPSOC_GLOBAL_CONF_MEM_CPY_START_ADDR_H … #define mmPSOC_GLOBAL_CONF_MEM_CPY_START_ADDR_L … #define mmPSOC_GLOBAL_CONF_MEM_CPY_DEST_ADDR_H … #define mmPSOC_GLOBAL_CONF_MEM_CPY_DEST_ADDR_L … #define mmPSOC_GLOBAL_CONF_MEM_CPY_CTRL2 … #define mmPSOC_GLOBAL_CONF_MEM_CPY_CONST … #define mmPSOC_GLOBAL_CONF_MEM_CPY_CURR_ADDR_H … #define mmPSOC_GLOBAL_CONF_MEM_CPY_CURR_ADDR_L … #define mmPSOC_GLOBAL_CONF_AXI_SPLIT_CFG … #define mmPSOC_GLOBAL_CONF_AXI_SPLIT_PROT_CFG1 … #define mmPSOC_GLOBAL_CONF_AXI_SPLIT_USER_CFG0 … #define mmPSOC_GLOBAL_CONF_AXI_SPLIT_USER_CFG1 … #define mmPSOC_GLOBAL_CONF_AXI_SPLIT_USER_CFG2 … #define mmPSOC_GLOBAL_CONF_AXI_SPLIT_USER_CFG3 … #define mmPSOC_GLOBAL_CONF_AXI_SPLIT_USER_CFG4 … #define mmPSOC_GLOBAL_CONF_LBW_ARUSER_OVRD … #define mmPSOC_GLOBAL_CONF_LBW_ARUSER_OVRD_EN … #define mmPSOC_GLOBAL_CONF_LBW_AWUSER_OVRD … #define mmPSOC_GLOBAL_CONF_LBW_AWUSER_OVRD_EN … #define mmPSOC_GLOBAL_CONF_MAIN_AXI_SPLIT_CFG2 … #define mmPSOC_GLOBAL_CONF_BOOTROM_AXI_SPLIT_CFG2 … #define mmPSOC_GLOBAL_CONF_AXI_SPLIT_INTR_CLEAR … #define mmPSOC_GLOBAL_CONF_MEM_CPY_PROT … #define mmPSOC_GLOBAL_CONF_ISOLATE_INPUTS … #define mmPSOC_GLOBAL_CONF_MESH_TO_BOOTROM_CTRL … #define mmPSOC_GLOBAL_CONF_ARC_JT_SEL … #define mmPSOC_GLOBAL_CONF_PLL_DUMP_CRTL … #define mmPSOC_GLOBAL_CONF_MEM_CPY_AXUSER … #define mmPSOC_GLOBAL_CONF_BTL_AXUSER … #define mmPSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL0 … #define mmPSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL1 … #define mmPSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL2 … #define mmPSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL3 … #define mmPSOC_GLOBAL_CONF_AXI_DRAIN_CTRL … #define mmPSOC_GLOBAL_CONF_AXI_DRAIN_TIMEOUT … #define mmPSOC_GLOBAL_CONF_AXI_DRAIN_INTR … #define mmPSOC_GLOBAL_CONF_BTL_STOP_SPI_CLK … #define mmPSOC_GLOBAL_CONF_ECO_INTR_CAUSE … #define mmPSOC_GLOBAL_CONF_ECO_INTR_CLEAR … #define mmPSOC_GLOBAL_CONF_ECO_INTR_MASK … #define mmPSOC_GLOBAL_CONF_DFT_APB_CONTROL … #endif /* ASIC_REG_PSOC_GLOBAL_CONF_REGS_H_ */
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