/* SPDX-License-Identifier: GPL-2.0 * * Copyright 2016-2020 HabanaLabs, Ltd. * All Rights Reserved. * */ /************************************ ** This is an auto-generated file ** ** DO NOT EDIT BELOW ** ************************************/ #ifndef ASIC_REG_XBAR_MID_0_REGS_H_ #define ASIC_REG_XBAR_MID_0_REGS_H_ /* ***************************************** * XBAR_MID_0 * (Prototype: XBAR) ***************************************** */ #define mmXBAR_MID_0_LBW_HIF0_BASE_ADDR … #define mmXBAR_MID_0_LBW_HIF0_ADDR_MASK … #define mmXBAR_MID_0_LBW_HIF1_BASE_ADDR … #define mmXBAR_MID_0_LBW_HIF1_ADDR_MASK … #define mmXBAR_MID_0_LBW_HMMU0_BASE_ADDR … #define mmXBAR_MID_0_LBW_HMMU0_ADDR_MASK … #define mmXBAR_MID_0_LBW_HMMU1_BASE_ADDR … #define mmXBAR_MID_0_LBW_HMMU1_ADDR_MASK … #define mmXBAR_MID_0_LBW_EDMA_BASE_ADDR0 … #define mmXBAR_MID_0_LBW_EDMA_ADDR_MASK0 … #define mmXBAR_MID_0_LBW_EDMA_BASE_ADDR1 … #define mmXBAR_MID_0_LBW_EDMA_ADDR_MASK1 … #define mmXBAR_MID_0_LBW_HBM_BASE_ADDR0 … #define mmXBAR_MID_0_LBW_HBM_ADDR_MASK0 … #define mmXBAR_MID_0_LBW_HBM_BASE_ADDR1 … #define mmXBAR_MID_0_LBW_HBM_ADDR_MASK1 … #define mmXBAR_MID_0_LBW_XBAR_BASE_ADDR0 … #define mmXBAR_MID_0_LBW_XBAR_ADDR_MASK0 … #define mmXBAR_MID_0_LBW_XBAR_BASE_ADDR1 … #define mmXBAR_MID_0_LBW_XBAR_ADDR_MASK1 … #define mmXBAR_MID_0_DBG_HIF0_BASE_ADDR … #define mmXBAR_MID_0_DBG_HIF0_ADDR_MASK … #define mmXBAR_MID_0_DBG_HIF1_BASE_ADDR … #define mmXBAR_MID_0_DBG_HIF1_ADDR_MASK … #define mmXBAR_MID_0_DBG_HMMU0_BASE_ADDR … #define mmXBAR_MID_0_DBG_HMMU0_ADDR_MASK … #define mmXBAR_MID_0_DBG_HMMU1_BASE_ADDR … #define mmXBAR_MID_0_DBG_HMMU1_ADDR_MASK … #define mmXBAR_MID_0_DBG_EDMA_BASE_ADDR0 … #define mmXBAR_MID_0_DBG_EDMA_ADDR_MASK0 … #define mmXBAR_MID_0_DBG_EDMA_BASE_ADDR1 … #define mmXBAR_MID_0_DBG_EDMA_ADDR_MASK1 … #define mmXBAR_MID_0_DBG_HBM_BASE_ADDR0 … #define mmXBAR_MID_0_DBG_HBM_ADDR_MASK0 … #define mmXBAR_MID_0_DBG_HBM_BASE_ADDR1 … #define mmXBAR_MID_0_DBG_HBM_ADDR_MASK1 … #define mmXBAR_MID_0_DBG_XBAR_BASE_ADDR0 … #define mmXBAR_MID_0_DBG_XBAR_ADDR_MASK0 … #define mmXBAR_MID_0_DBG_XBAR_BASE_ADDR1 … #define mmXBAR_MID_0_DBG_XBAR_ADDR_MASK1 … #define mmXBAR_MID_0_LBW_INTERNAL_ADDR_RGF … #define mmXBAR_MID_0_DBG_INTERNAL_ADDR_FUN … #define mmXBAR_MID_0_EMEM_HBM_BIT_LOCATION … #define mmXBAR_MID_0_EMEM_PC_BIT_LOCATION … #define mmXBAR_MID_0_HIF_WR_RS_CH_LOCATION … #define mmXBAR_MID_0_HBW_MST_ARB_WEIGHT … #define mmXBAR_MID_0_MMU_PC_IDX_MAP_0 … #define mmXBAR_MID_0_MMU_PC_IDX_MAP_1 … #define mmXBAR_MID_0_MMU_RD_LL_ARB_0 … #define mmXBAR_MID_0_MMU_RD_LL_ARB_1 … #define mmXBAR_MID_0_MMU_WR_LL_ARB_0 … #define mmXBAR_MID_0_MMU_WR_LL_ARB_1 … #define mmXBAR_MID_0_HBM_USER_RESP_OVR_0 … #define mmXBAR_MID_0_HBM_USER_RESP_OVR_1 … #define mmXBAR_MID_0_RL_RD_0 … #define mmXBAR_MID_0_RL_RD_1 … #define mmXBAR_MID_0_RL_RD_2 … #define mmXBAR_MID_0_RL_RD_3 … #define mmXBAR_MID_0_RL_RD_4 … #define mmXBAR_MID_0_RL_RD_5 … #define mmXBAR_MID_0_RL_RD_6 … #define mmXBAR_MID_0_RL_RD_7 … #define mmXBAR_MID_0_RL_RD_8 … #define mmXBAR_MID_0_RL_RD_9 … #define mmXBAR_MID_0_RL_RD_10 … #define mmXBAR_MID_0_RL_RD_11 … #define mmXBAR_MID_0_RL_WR_0 … #define mmXBAR_MID_0_RL_WR_1 … #define mmXBAR_MID_0_RL_WR_2 … #define mmXBAR_MID_0_RL_WR_3 … #define mmXBAR_MID_0_RL_WR_4 … #define mmXBAR_MID_0_RL_WR_5 … #define mmXBAR_MID_0_RL_WR_6 … #define mmXBAR_MID_0_RL_WR_7 … #define mmXBAR_MID_0_RL_WR_8 … #define mmXBAR_MID_0_RL_WR_9 … #define mmXBAR_MID_0_RL_WR_10 … #define mmXBAR_MID_0_RL_WR_11 … #define mmXBAR_MID_0_E2E_CRDT_SLV_0 … #define mmXBAR_MID_0_E2E_CRDT_SLV_1 … #define mmXBAR_MID_0_E2E_CRDT_SLV_2 … #define mmXBAR_MID_0_E2E_CRDT_DEBUG … #define mmXBAR_MID_0_UPSCALE … #define mmXBAR_MID_0_DOWN_CONV … #define mmXBAR_MID_0_DOWN_CONV_LFSR_EN … #define mmXBAR_MID_0_DOWN_CONV_LFSR_SET_VLD … #define mmXBAR_MID_0_DOWN_CONV_LFSR_SET_VALUE … #define mmXBAR_MID_0_DOWN_CONV_LFSR_CFG_POLY … #endif /* ASIC_REG_XBAR_MID_0_REGS_H_ */
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