/* SPDX-License-Identifier: GPL-2.0 * * Copyright 2016-2020 HabanaLabs, Ltd. * All Rights Reserved. * */ /************************************ ** This is an auto-generated file ** ** DO NOT EDIT BELOW ** ************************************/ #ifndef ASIC_REG_DCORE0_SYNC_MNGR_GLBL_REGS_H_ #define ASIC_REG_DCORE0_SYNC_MNGR_GLBL_REGS_H_ /* ***************************************** * DCORE0_SYNC_MNGR_GLBL * (Prototype: SOB_GLBL) ***************************************** */ #define mmDCORE0_SYNC_MNGR_GLBL_SM_SEI_MASK … #define mmDCORE0_SYNC_MNGR_GLBL_SM_SEI_CAUSE … #define mmDCORE0_SYNC_MNGR_GLBL_L2H_CPMR_L … #define mmDCORE0_SYNC_MNGR_GLBL_L2H_CPMR_H … #define mmDCORE0_SYNC_MNGR_GLBL_L2H_MASK_L … #define mmDCORE0_SYNC_MNGR_GLBL_L2H_MASK_H … #define mmDCORE0_SYNC_MNGR_GLBL_ASID_SEC … #define mmDCORE0_SYNC_MNGR_GLBL_ASID_PRIV_ONLY … #define mmDCORE0_SYNC_MNGR_GLBL_LBW_DELAY … #define mmDCORE0_SYNC_MNGR_GLBL_PI_SIZE … #define mmDCORE0_SYNC_MNGR_GLBL_SOB_ONLY … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_INTR … #define mmDCORE0_SYNC_MNGR_GLBL_ASID_NONE_SEC_PRIV … #define mmDCORE0_SYNC_MNGR_GLBL_PI_INC_MODE_SIZE … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_0 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_1 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_2 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_3 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_4 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_5 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_6 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_7 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_8 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_9 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_10 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_11 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_12 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_13 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_14 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_15 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_16 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_17 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_18 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_19 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_20 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_21 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_22 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_23 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_24 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_25 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_26 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_27 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_28 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_29 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_30 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_31 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_32 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_33 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_34 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_35 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_36 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_37 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_38 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_39 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_40 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_41 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_42 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_43 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_44 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_45 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_46 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_47 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_48 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_49 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_50 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_51 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_52 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_53 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_54 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_55 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_56 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_57 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_58 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_59 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_60 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_61 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_62 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_63 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_0 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_1 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_2 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_3 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_4 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_5 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_6 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_7 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_8 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_9 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_10 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_11 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_12 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_13 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_14 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_15 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_16 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_17 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_18 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_19 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_20 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_21 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_22 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_23 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_24 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_25 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_26 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_27 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_28 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_29 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_30 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_31 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_32 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_33 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_34 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_35 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_36 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_37 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_38 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_39 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_40 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_41 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_42 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_43 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_44 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_45 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_46 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_47 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_48 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_49 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_50 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_51 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_52 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_53 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_54 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_55 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_56 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_57 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_58 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_59 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_60 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_61 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_62 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_63 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_0 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_1 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_2 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_3 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_4 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_5 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_6 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_7 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_8 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_9 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_10 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_11 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_12 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_13 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_14 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_15 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_16 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_17 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_18 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_19 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_20 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_21 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_22 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_23 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_24 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_25 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_26 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_27 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_28 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_29 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_30 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_31 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_32 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_33 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_34 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_35 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_36 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_37 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_38 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_39 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_40 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_41 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_42 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_43 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_44 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_45 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_46 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_47 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_48 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_49 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_50 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_51 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_52 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_53 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_54 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_55 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_56 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_57 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_58 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_59 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_60 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_61 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_62 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_63 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_0 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_1 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_2 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_3 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_4 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_5 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_6 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_7 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_8 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_9 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_10 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_11 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_12 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_13 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_14 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_15 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_16 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_17 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_18 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_19 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_20 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_21 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_22 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_23 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_24 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_25 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_26 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_27 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_28 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_29 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_30 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_31 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_32 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_33 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_34 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_35 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_36 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_37 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_38 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_39 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_40 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_41 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_42 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_43 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_44 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_45 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_46 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_47 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_48 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_49 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_50 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_51 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_52 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_53 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_54 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_55 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_56 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_57 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_58 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_59 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_60 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_61 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_62 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_63 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_SEC_0 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_SEC_1 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_SEC_2 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_SEC_3 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_SEC_4 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_SEC_5 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_SEC_6 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_SEC_7 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_SEC_8 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_SEC_9 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_SEC_10 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_SEC_11 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_SEC_12 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_SEC_13 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_SEC_14 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_SEC_15 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_SEC_16 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_SEC_17 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_SEC_18 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_SEC_19 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_SEC_20 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_SEC_21 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_SEC_22 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_SEC_23 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_SEC_24 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_SEC_25 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_SEC_26 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_SEC_27 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_SEC_28 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_SEC_29 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_SEC_30 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_SEC_31 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_SEC_32 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_SEC_33 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_SEC_34 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_SEC_35 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_SEC_36 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_SEC_37 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_SEC_38 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_SEC_39 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_SEC_40 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_SEC_41 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_SEC_42 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_SEC_43 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_SEC_44 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_SEC_45 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_SEC_46 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_SEC_47 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_SEC_48 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_SEC_49 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_SEC_50 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_SEC_51 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_SEC_52 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_SEC_53 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_SEC_54 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_SEC_55 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_SEC_56 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_SEC_57 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_SEC_58 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_SEC_59 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_SEC_60 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_SEC_61 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_SEC_62 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_SEC_63 … #define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_0 … #define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_1 … #define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_2 … #define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_3 … #define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_4 … #define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_5 … #define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_6 … #define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_7 … #define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_8 … #define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_9 … #define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_10 … #define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_11 … #define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_12 … #define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_13 … #define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_14 … #define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_15 … #define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_16 … #define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_17 … #define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_18 … #define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_19 … #define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_20 … #define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_21 … #define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_22 … #define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_23 … #define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_24 … #define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_25 … #define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_26 … #define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_27 … #define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_28 … #define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_29 … #define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_30 … #define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_31 … #define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_32 … #define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_33 … #define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_34 … #define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_35 … #define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_36 … #define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_37 … #define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_38 … #define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_39 … #define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_40 … #define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_41 … #define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_42 … #define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_43 … #define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_44 … #define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_45 … #define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_46 … #define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_47 … #define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_48 … #define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_49 … #define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_50 … #define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_51 … #define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_52 … #define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_53 … #define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_54 … #define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_55 … #define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_56 … #define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_57 … #define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_58 … #define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_59 … #define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_60 … #define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_61 … #define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_62 … #define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_63 … #define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_0 … #define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_1 … #define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_2 … #define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_3 … #define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_4 … #define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_5 … #define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_6 … #define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_7 … #define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_8 … #define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_9 … #define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_10 … #define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_11 … #define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_12 … #define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_13 … #define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_14 … #define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_15 … #define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_16 … #define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_17 … #define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_18 … #define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_19 … #define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_20 … #define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_21 … #define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_22 … #define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_23 … #define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_24 … #define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_25 … #define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_26 … #define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_27 … #define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_28 … #define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_29 … #define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_30 … #define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_31 … #define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_32 … #define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_33 … #define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_34 … #define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_35 … #define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_36 … #define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_37 … #define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_38 … #define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_39 … #define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_40 … #define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_41 … #define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_42 … #define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_43 … #define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_44 … #define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_45 … #define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_46 … #define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_47 … #define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_48 … #define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_49 … #define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_50 … #define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_51 … #define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_52 … #define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_53 … #define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_54 … #define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_55 … #define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_56 … #define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_57 … #define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_58 … #define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_59 … #define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_60 … #define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_61 … #define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_62 … #define mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_63 … #define mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_0 … #define mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_1 … #define mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_2 … #define mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_3 … #define mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_4 … #define mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_5 … #define mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_6 … #define mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_7 … #define mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_8 … #define mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_9 … #define mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_10 … #define mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_11 … #define mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_12 … #define mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_13 … #define mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_14 … #define mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_15 … #define mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_16 … #define mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_17 … #define mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_18 … #define mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_19 … #define mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_20 … #define mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_21 … #define mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_22 … #define mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_23 … #define mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_24 … #define mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_25 … #define mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_26 … #define mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_27 … #define mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_28 … #define mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_29 … #define mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_30 … #define mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_31 … #define mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_32 … #define mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_33 … #define mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_34 … #define mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_35 … #define mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_36 … #define mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_37 … #define mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_38 … #define mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_39 … #define mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_40 … #define mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_41 … #define mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_42 … #define mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_43 … #define mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_44 … #define mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_45 … #define mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_46 … #define mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_47 … #define mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_48 … #define mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_49 … #define mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_50 … #define mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_51 … #define mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_52 … #define mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_53 … #define mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_54 … #define mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_55 … #define mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_56 … #define mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_57 … #define mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_58 … #define mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_59 … #define mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_60 … #define mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_61 … #define mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_62 … #define mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_63 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_0 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_1 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_2 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_3 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_4 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_5 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_6 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_7 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_8 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_9 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_10 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_11 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_12 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_13 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_14 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_15 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_16 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_17 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_18 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_19 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_20 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_21 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_22 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_23 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_24 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_25 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_26 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_27 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_28 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_29 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_30 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_31 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_32 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_33 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_34 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_35 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_36 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_37 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_38 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_39 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_40 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_41 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_42 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_43 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_44 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_45 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_46 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_47 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_48 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_49 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_50 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_51 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_52 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_53 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_54 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_55 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_56 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_57 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_58 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_59 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_60 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_61 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_62 … #define mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_63 … #endif /* ASIC_REG_DCORE0_SYNC_MNGR_GLBL_REGS_H_ */
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