#ifndef ASIC_REG_PDMA0_QM_AXUSER_SECURED_REGS_H_
#define ASIC_REG_PDMA0_QM_AXUSER_SECURED_REGS_H_
#define mmPDMA0_QM_AXUSER_SECURED_HB_ASID …
#define mmPDMA0_QM_AXUSER_SECURED_HB_MMU_BP …
#define mmPDMA0_QM_AXUSER_SECURED_HB_STRONG_ORDER …
#define mmPDMA0_QM_AXUSER_SECURED_HB_NO_SNOOP …
#define mmPDMA0_QM_AXUSER_SECURED_HB_WR_REDUCTION …
#define mmPDMA0_QM_AXUSER_SECURED_HB_RD_ATOMIC …
#define mmPDMA0_QM_AXUSER_SECURED_HB_QOS …
#define mmPDMA0_QM_AXUSER_SECURED_HB_RSVD …
#define mmPDMA0_QM_AXUSER_SECURED_HB_EMEM_CPAGE …
#define mmPDMA0_QM_AXUSER_SECURED_HB_CORE …
#define mmPDMA0_QM_AXUSER_SECURED_E2E_COORD …
#define mmPDMA0_QM_AXUSER_SECURED_HB_WR_OVRD_LO …
#define mmPDMA0_QM_AXUSER_SECURED_HB_WR_OVRD_HI …
#define mmPDMA0_QM_AXUSER_SECURED_HB_RD_OVRD_LO …
#define mmPDMA0_QM_AXUSER_SECURED_HB_RD_OVRD_HI …
#define mmPDMA0_QM_AXUSER_SECURED_LB_COORD …
#define mmPDMA0_QM_AXUSER_SECURED_LB_LOCK …
#define mmPDMA0_QM_AXUSER_SECURED_LB_RSVD …
#define mmPDMA0_QM_AXUSER_SECURED_LB_OVRD …
#endif