#ifndef ASIC_REG_PDMA1_QM_AXUSER_NONSECURED_REGS_H_
#define ASIC_REG_PDMA1_QM_AXUSER_NONSECURED_REGS_H_
#define mmPDMA1_QM_AXUSER_NONSECURED_HB_ASID …
#define mmPDMA1_QM_AXUSER_NONSECURED_HB_MMU_BP …
#define mmPDMA1_QM_AXUSER_NONSECURED_HB_STRONG_ORDER …
#define mmPDMA1_QM_AXUSER_NONSECURED_HB_NO_SNOOP …
#define mmPDMA1_QM_AXUSER_NONSECURED_HB_WR_REDUCTION …
#define mmPDMA1_QM_AXUSER_NONSECURED_HB_RD_ATOMIC …
#define mmPDMA1_QM_AXUSER_NONSECURED_HB_QOS …
#define mmPDMA1_QM_AXUSER_NONSECURED_HB_RSVD …
#define mmPDMA1_QM_AXUSER_NONSECURED_HB_EMEM_CPAGE …
#define mmPDMA1_QM_AXUSER_NONSECURED_HB_CORE …
#define mmPDMA1_QM_AXUSER_NONSECURED_E2E_COORD …
#define mmPDMA1_QM_AXUSER_NONSECURED_HB_WR_OVRD_LO …
#define mmPDMA1_QM_AXUSER_NONSECURED_HB_WR_OVRD_HI …
#define mmPDMA1_QM_AXUSER_NONSECURED_HB_RD_OVRD_LO …
#define mmPDMA1_QM_AXUSER_NONSECURED_HB_RD_OVRD_HI …
#define mmPDMA1_QM_AXUSER_NONSECURED_LB_COORD …
#define mmPDMA1_QM_AXUSER_NONSECURED_LB_LOCK …
#define mmPDMA1_QM_AXUSER_NONSECURED_LB_RSVD …
#define mmPDMA1_QM_AXUSER_NONSECURED_LB_OVRD …
#endif