/* SPDX-License-Identifier: GPL-2.0 * * Copyright 2016-2020 HabanaLabs, Ltd. * All Rights Reserved. * */ /************************************ ** This is an auto-generated file ** ** DO NOT EDIT BELOW ** ************************************/ #ifndef ASIC_REG_DCORE0_TPC0_QM_REGS_H_ #define ASIC_REG_DCORE0_TPC0_QM_REGS_H_ /* ***************************************** * DCORE0_TPC0_QM * (Prototype: QMAN) ***************************************** */ #define mmDCORE0_TPC0_QM_GLBL_CFG0 … #define mmDCORE0_TPC0_QM_GLBL_CFG1 … #define mmDCORE0_TPC0_QM_GLBL_CFG2 … #define mmDCORE0_TPC0_QM_GLBL_ERR_CFG … #define mmDCORE0_TPC0_QM_GLBL_ERR_CFG1 … #define mmDCORE0_TPC0_QM_GLBL_ERR_ARC_HALT_EN … #define mmDCORE0_TPC0_QM_GLBL_AXCACHE … #define mmDCORE0_TPC0_QM_GLBL_STS0 … #define mmDCORE0_TPC0_QM_GLBL_STS1 … #define mmDCORE0_TPC0_QM_GLBL_ERR_STS_0 … #define mmDCORE0_TPC0_QM_GLBL_ERR_STS_1 … #define mmDCORE0_TPC0_QM_GLBL_ERR_STS_2 … #define mmDCORE0_TPC0_QM_GLBL_ERR_STS_3 … #define mmDCORE0_TPC0_QM_GLBL_ERR_STS_4 … #define mmDCORE0_TPC0_QM_GLBL_ERR_MSG_EN_0 … #define mmDCORE0_TPC0_QM_GLBL_ERR_MSG_EN_1 … #define mmDCORE0_TPC0_QM_GLBL_ERR_MSG_EN_2 … #define mmDCORE0_TPC0_QM_GLBL_ERR_MSG_EN_3 … #define mmDCORE0_TPC0_QM_GLBL_ERR_MSG_EN_4 … #define mmDCORE0_TPC0_QM_GLBL_PROT … #define mmDCORE0_TPC0_QM_PQ_BASE_LO_0 … #define mmDCORE0_TPC0_QM_PQ_BASE_LO_1 … #define mmDCORE0_TPC0_QM_PQ_BASE_LO_2 … #define mmDCORE0_TPC0_QM_PQ_BASE_LO_3 … #define mmDCORE0_TPC0_QM_PQ_BASE_HI_0 … #define mmDCORE0_TPC0_QM_PQ_BASE_HI_1 … #define mmDCORE0_TPC0_QM_PQ_BASE_HI_2 … #define mmDCORE0_TPC0_QM_PQ_BASE_HI_3 … #define mmDCORE0_TPC0_QM_PQ_SIZE_0 … #define mmDCORE0_TPC0_QM_PQ_SIZE_1 … #define mmDCORE0_TPC0_QM_PQ_SIZE_2 … #define mmDCORE0_TPC0_QM_PQ_SIZE_3 … #define mmDCORE0_TPC0_QM_PQ_PI_0 … #define mmDCORE0_TPC0_QM_PQ_PI_1 … #define mmDCORE0_TPC0_QM_PQ_PI_2 … #define mmDCORE0_TPC0_QM_PQ_PI_3 … #define mmDCORE0_TPC0_QM_PQ_CI_0 … #define mmDCORE0_TPC0_QM_PQ_CI_1 … #define mmDCORE0_TPC0_QM_PQ_CI_2 … #define mmDCORE0_TPC0_QM_PQ_CI_3 … #define mmDCORE0_TPC0_QM_PQ_CFG0_0 … #define mmDCORE0_TPC0_QM_PQ_CFG0_1 … #define mmDCORE0_TPC0_QM_PQ_CFG0_2 … #define mmDCORE0_TPC0_QM_PQ_CFG0_3 … #define mmDCORE0_TPC0_QM_PQ_CFG1_0 … #define mmDCORE0_TPC0_QM_PQ_CFG1_1 … #define mmDCORE0_TPC0_QM_PQ_CFG1_2 … #define mmDCORE0_TPC0_QM_PQ_CFG1_3 … #define mmDCORE0_TPC0_QM_PQ_STS0_0 … #define mmDCORE0_TPC0_QM_PQ_STS0_1 … #define mmDCORE0_TPC0_QM_PQ_STS0_2 … #define mmDCORE0_TPC0_QM_PQ_STS0_3 … #define mmDCORE0_TPC0_QM_PQ_STS1_0 … #define mmDCORE0_TPC0_QM_PQ_STS1_1 … #define mmDCORE0_TPC0_QM_PQ_STS1_2 … #define mmDCORE0_TPC0_QM_PQ_STS1_3 … #define mmDCORE0_TPC0_QM_CQ_CFG0_0 … #define mmDCORE0_TPC0_QM_CQ_CFG0_1 … #define mmDCORE0_TPC0_QM_CQ_CFG0_2 … #define mmDCORE0_TPC0_QM_CQ_CFG0_3 … #define mmDCORE0_TPC0_QM_CQ_CFG0_4 … #define mmDCORE0_TPC0_QM_CQ_STS0_0 … #define mmDCORE0_TPC0_QM_CQ_STS0_1 … #define mmDCORE0_TPC0_QM_CQ_STS0_2 … #define mmDCORE0_TPC0_QM_CQ_STS0_3 … #define mmDCORE0_TPC0_QM_CQ_STS0_4 … #define mmDCORE0_TPC0_QM_CQ_CFG1_0 … #define mmDCORE0_TPC0_QM_CQ_CFG1_1 … #define mmDCORE0_TPC0_QM_CQ_CFG1_2 … #define mmDCORE0_TPC0_QM_CQ_CFG1_3 … #define mmDCORE0_TPC0_QM_CQ_CFG1_4 … #define mmDCORE0_TPC0_QM_CQ_STS1_0 … #define mmDCORE0_TPC0_QM_CQ_STS1_1 … #define mmDCORE0_TPC0_QM_CQ_STS1_2 … #define mmDCORE0_TPC0_QM_CQ_STS1_3 … #define mmDCORE0_TPC0_QM_CQ_STS1_4 … #define mmDCORE0_TPC0_QM_CQ_PTR_LO_0 … #define mmDCORE0_TPC0_QM_CQ_PTR_HI_0 … #define mmDCORE0_TPC0_QM_CQ_TSIZE_0 … #define mmDCORE0_TPC0_QM_CQ_CTL_0 … #define mmDCORE0_TPC0_QM_CQ_PTR_LO_1 … #define mmDCORE0_TPC0_QM_CQ_PTR_HI_1 … #define mmDCORE0_TPC0_QM_CQ_TSIZE_1 … #define mmDCORE0_TPC0_QM_CQ_CTL_1 … #define mmDCORE0_TPC0_QM_CQ_PTR_LO_2 … #define mmDCORE0_TPC0_QM_CQ_PTR_HI_2 … #define mmDCORE0_TPC0_QM_CQ_TSIZE_2 … #define mmDCORE0_TPC0_QM_CQ_CTL_2 … #define mmDCORE0_TPC0_QM_CQ_PTR_LO_3 … #define mmDCORE0_TPC0_QM_CQ_PTR_HI_3 … #define mmDCORE0_TPC0_QM_CQ_TSIZE_3 … #define mmDCORE0_TPC0_QM_CQ_CTL_3 … #define mmDCORE0_TPC0_QM_CQ_PTR_LO_4 … #define mmDCORE0_TPC0_QM_CQ_PTR_HI_4 … #define mmDCORE0_TPC0_QM_CQ_TSIZE_4 … #define mmDCORE0_TPC0_QM_CQ_CTL_4 … #define mmDCORE0_TPC0_QM_CQ_TSIZE_STS_0 … #define mmDCORE0_TPC0_QM_CQ_TSIZE_STS_1 … #define mmDCORE0_TPC0_QM_CQ_TSIZE_STS_2 … #define mmDCORE0_TPC0_QM_CQ_TSIZE_STS_3 … #define mmDCORE0_TPC0_QM_CQ_TSIZE_STS_4 … #define mmDCORE0_TPC0_QM_CQ_PTR_LO_STS_0 … #define mmDCORE0_TPC0_QM_CQ_PTR_LO_STS_1 … #define mmDCORE0_TPC0_QM_CQ_PTR_LO_STS_2 … #define mmDCORE0_TPC0_QM_CQ_PTR_LO_STS_3 … #define mmDCORE0_TPC0_QM_CQ_PTR_LO_STS_4 … #define mmDCORE0_TPC0_QM_CQ_PTR_HI_STS_0 … #define mmDCORE0_TPC0_QM_CQ_PTR_HI_STS_1 … #define mmDCORE0_TPC0_QM_CQ_PTR_HI_STS_2 … #define mmDCORE0_TPC0_QM_CQ_PTR_HI_STS_3 … #define mmDCORE0_TPC0_QM_CQ_PTR_HI_STS_4 … #define mmDCORE0_TPC0_QM_CQ_IFIFO_STS_0 … #define mmDCORE0_TPC0_QM_CQ_IFIFO_STS_1 … #define mmDCORE0_TPC0_QM_CQ_IFIFO_STS_2 … #define mmDCORE0_TPC0_QM_CQ_IFIFO_STS_3 … #define mmDCORE0_TPC0_QM_CQ_IFIFO_STS_4 … #define mmDCORE0_TPC0_QM_CP_MSG_BASE0_ADDR_LO_0 … #define mmDCORE0_TPC0_QM_CP_MSG_BASE0_ADDR_LO_1 … #define mmDCORE0_TPC0_QM_CP_MSG_BASE0_ADDR_LO_2 … #define mmDCORE0_TPC0_QM_CP_MSG_BASE0_ADDR_LO_3 … #define mmDCORE0_TPC0_QM_CP_MSG_BASE0_ADDR_LO_4 … #define mmDCORE0_TPC0_QM_CP_MSG_BASE0_ADDR_HI_0 … #define mmDCORE0_TPC0_QM_CP_MSG_BASE0_ADDR_HI_1 … #define mmDCORE0_TPC0_QM_CP_MSG_BASE0_ADDR_HI_2 … #define mmDCORE0_TPC0_QM_CP_MSG_BASE0_ADDR_HI_3 … #define mmDCORE0_TPC0_QM_CP_MSG_BASE0_ADDR_HI_4 … #define mmDCORE0_TPC0_QM_CP_MSG_BASE1_ADDR_LO_0 … #define mmDCORE0_TPC0_QM_CP_MSG_BASE1_ADDR_LO_1 … #define mmDCORE0_TPC0_QM_CP_MSG_BASE1_ADDR_LO_2 … #define mmDCORE0_TPC0_QM_CP_MSG_BASE1_ADDR_LO_3 … #define mmDCORE0_TPC0_QM_CP_MSG_BASE1_ADDR_LO_4 … #define mmDCORE0_TPC0_QM_CP_MSG_BASE1_ADDR_HI_0 … #define mmDCORE0_TPC0_QM_CP_MSG_BASE1_ADDR_HI_1 … #define mmDCORE0_TPC0_QM_CP_MSG_BASE1_ADDR_HI_2 … #define mmDCORE0_TPC0_QM_CP_MSG_BASE1_ADDR_HI_3 … #define mmDCORE0_TPC0_QM_CP_MSG_BASE1_ADDR_HI_4 … #define mmDCORE0_TPC0_QM_CP_MSG_BASE2_ADDR_LO_0 … #define mmDCORE0_TPC0_QM_CP_MSG_BASE2_ADDR_LO_1 … #define mmDCORE0_TPC0_QM_CP_MSG_BASE2_ADDR_LO_2 … #define mmDCORE0_TPC0_QM_CP_MSG_BASE2_ADDR_LO_3 … #define mmDCORE0_TPC0_QM_CP_MSG_BASE2_ADDR_LO_4 … #define mmDCORE0_TPC0_QM_CP_MSG_BASE2_ADDR_HI_0 … #define mmDCORE0_TPC0_QM_CP_MSG_BASE2_ADDR_HI_1 … #define mmDCORE0_TPC0_QM_CP_MSG_BASE2_ADDR_HI_2 … #define mmDCORE0_TPC0_QM_CP_MSG_BASE2_ADDR_HI_3 … #define mmDCORE0_TPC0_QM_CP_MSG_BASE2_ADDR_HI_4 … #define mmDCORE0_TPC0_QM_CP_MSG_BASE3_ADDR_LO_0 … #define mmDCORE0_TPC0_QM_CP_MSG_BASE3_ADDR_LO_1 … #define mmDCORE0_TPC0_QM_CP_MSG_BASE3_ADDR_LO_2 … #define mmDCORE0_TPC0_QM_CP_MSG_BASE3_ADDR_LO_3 … #define mmDCORE0_TPC0_QM_CP_MSG_BASE3_ADDR_LO_4 … #define mmDCORE0_TPC0_QM_CP_MSG_BASE3_ADDR_HI_0 … #define mmDCORE0_TPC0_QM_CP_MSG_BASE3_ADDR_HI_1 … #define mmDCORE0_TPC0_QM_CP_MSG_BASE3_ADDR_HI_2 … #define mmDCORE0_TPC0_QM_CP_MSG_BASE3_ADDR_HI_3 … #define mmDCORE0_TPC0_QM_CP_MSG_BASE3_ADDR_HI_4 … #define mmDCORE0_TPC0_QM_CP_FENCE0_RDATA_0 … #define mmDCORE0_TPC0_QM_CP_FENCE0_RDATA_1 … #define mmDCORE0_TPC0_QM_CP_FENCE0_RDATA_2 … #define mmDCORE0_TPC0_QM_CP_FENCE0_RDATA_3 … #define mmDCORE0_TPC0_QM_CP_FENCE0_RDATA_4 … #define mmDCORE0_TPC0_QM_CP_FENCE1_RDATA_0 … #define mmDCORE0_TPC0_QM_CP_FENCE1_RDATA_1 … #define mmDCORE0_TPC0_QM_CP_FENCE1_RDATA_2 … #define mmDCORE0_TPC0_QM_CP_FENCE1_RDATA_3 … #define mmDCORE0_TPC0_QM_CP_FENCE1_RDATA_4 … #define mmDCORE0_TPC0_QM_CP_FENCE2_RDATA_0 … #define mmDCORE0_TPC0_QM_CP_FENCE2_RDATA_1 … #define mmDCORE0_TPC0_QM_CP_FENCE2_RDATA_2 … #define mmDCORE0_TPC0_QM_CP_FENCE2_RDATA_3 … #define mmDCORE0_TPC0_QM_CP_FENCE2_RDATA_4 … #define mmDCORE0_TPC0_QM_CP_FENCE3_RDATA_0 … #define mmDCORE0_TPC0_QM_CP_FENCE3_RDATA_1 … #define mmDCORE0_TPC0_QM_CP_FENCE3_RDATA_2 … #define mmDCORE0_TPC0_QM_CP_FENCE3_RDATA_3 … #define mmDCORE0_TPC0_QM_CP_FENCE3_RDATA_4 … #define mmDCORE0_TPC0_QM_CP_FENCE0_CNT_0 … #define mmDCORE0_TPC0_QM_CP_FENCE0_CNT_1 … #define mmDCORE0_TPC0_QM_CP_FENCE0_CNT_2 … #define mmDCORE0_TPC0_QM_CP_FENCE0_CNT_3 … #define mmDCORE0_TPC0_QM_CP_FENCE0_CNT_4 … #define mmDCORE0_TPC0_QM_CP_FENCE1_CNT_0 … #define mmDCORE0_TPC0_QM_CP_FENCE1_CNT_1 … #define mmDCORE0_TPC0_QM_CP_FENCE1_CNT_2 … #define mmDCORE0_TPC0_QM_CP_FENCE1_CNT_3 … #define mmDCORE0_TPC0_QM_CP_FENCE1_CNT_4 … #define mmDCORE0_TPC0_QM_CP_FENCE2_CNT_0 … #define mmDCORE0_TPC0_QM_CP_FENCE2_CNT_1 … #define mmDCORE0_TPC0_QM_CP_FENCE2_CNT_2 … #define mmDCORE0_TPC0_QM_CP_FENCE2_CNT_3 … #define mmDCORE0_TPC0_QM_CP_FENCE2_CNT_4 … #define mmDCORE0_TPC0_QM_CP_FENCE3_CNT_0 … #define mmDCORE0_TPC0_QM_CP_FENCE3_CNT_1 … #define mmDCORE0_TPC0_QM_CP_FENCE3_CNT_2 … #define mmDCORE0_TPC0_QM_CP_FENCE3_CNT_3 … #define mmDCORE0_TPC0_QM_CP_FENCE3_CNT_4 … #define mmDCORE0_TPC0_QM_CP_BARRIER_CFG … #define mmDCORE0_TPC0_QM_CP_LDMA_SRC_BASE_LO_OFFSET … #define mmDCORE0_TPC0_QM_CP_LDMA_DST_BASE_LO_OFFSET … #define mmDCORE0_TPC0_QM_CP_LDMA_TSIZE_OFFSET … #define mmDCORE0_TPC0_QM_CP_CQ_PTR_LO_OFFSET_0 … #define mmDCORE0_TPC0_QM_CP_CQ_PTR_LO_OFFSET_1 … #define mmDCORE0_TPC0_QM_CP_CQ_PTR_LO_OFFSET_2 … #define mmDCORE0_TPC0_QM_CP_CQ_PTR_LO_OFFSET_3 … #define mmDCORE0_TPC0_QM_CP_CQ_PTR_LO_OFFSET_4 … #define mmDCORE0_TPC0_QM_CP_STS_0 … #define mmDCORE0_TPC0_QM_CP_STS_1 … #define mmDCORE0_TPC0_QM_CP_STS_2 … #define mmDCORE0_TPC0_QM_CP_STS_3 … #define mmDCORE0_TPC0_QM_CP_STS_4 … #define mmDCORE0_TPC0_QM_CP_CURRENT_INST_LO_0 … #define mmDCORE0_TPC0_QM_CP_CURRENT_INST_LO_1 … #define mmDCORE0_TPC0_QM_CP_CURRENT_INST_LO_2 … #define mmDCORE0_TPC0_QM_CP_CURRENT_INST_LO_3 … #define mmDCORE0_TPC0_QM_CP_CURRENT_INST_LO_4 … #define mmDCORE0_TPC0_QM_CP_CURRENT_INST_HI_0 … #define mmDCORE0_TPC0_QM_CP_CURRENT_INST_HI_1 … #define mmDCORE0_TPC0_QM_CP_CURRENT_INST_HI_2 … #define mmDCORE0_TPC0_QM_CP_CURRENT_INST_HI_3 … #define mmDCORE0_TPC0_QM_CP_CURRENT_INST_HI_4 … #define mmDCORE0_TPC0_QM_CP_PRED_0 … #define mmDCORE0_TPC0_QM_CP_PRED_1 … #define mmDCORE0_TPC0_QM_CP_PRED_2 … #define mmDCORE0_TPC0_QM_CP_PRED_3 … #define mmDCORE0_TPC0_QM_CP_PRED_4 … #define mmDCORE0_TPC0_QM_CP_PRED_UPEN_0 … #define mmDCORE0_TPC0_QM_CP_PRED_UPEN_1 … #define mmDCORE0_TPC0_QM_CP_PRED_UPEN_2 … #define mmDCORE0_TPC0_QM_CP_PRED_UPEN_3 … #define mmDCORE0_TPC0_QM_CP_PRED_UPEN_4 … #define mmDCORE0_TPC0_QM_CP_DBG_0_0 … #define mmDCORE0_TPC0_QM_CP_DBG_0_1 … #define mmDCORE0_TPC0_QM_CP_DBG_0_2 … #define mmDCORE0_TPC0_QM_CP_DBG_0_3 … #define mmDCORE0_TPC0_QM_CP_DBG_0_4 … #define mmDCORE0_TPC0_QM_CP_CPDMA_UP_CRED_0 … #define mmDCORE0_TPC0_QM_CP_CPDMA_UP_CRED_1 … #define mmDCORE0_TPC0_QM_CP_CPDMA_UP_CRED_2 … #define mmDCORE0_TPC0_QM_CP_CPDMA_UP_CRED_3 … #define mmDCORE0_TPC0_QM_CP_CPDMA_UP_CRED_4 … #define mmDCORE0_TPC0_QM_CP_IN_DATA_LO_0 … #define mmDCORE0_TPC0_QM_CP_IN_DATA_LO_1 … #define mmDCORE0_TPC0_QM_CP_IN_DATA_LO_2 … #define mmDCORE0_TPC0_QM_CP_IN_DATA_LO_3 … #define mmDCORE0_TPC0_QM_CP_IN_DATA_LO_4 … #define mmDCORE0_TPC0_QM_CP_IN_DATA_HI_0 … #define mmDCORE0_TPC0_QM_CP_IN_DATA_HI_1 … #define mmDCORE0_TPC0_QM_CP_IN_DATA_HI_2 … #define mmDCORE0_TPC0_QM_CP_IN_DATA_HI_3 … #define mmDCORE0_TPC0_QM_CP_IN_DATA_HI_4 … #define mmDCORE0_TPC0_QM_PQC_HBW_BASE_LO_0 … #define mmDCORE0_TPC0_QM_PQC_HBW_BASE_LO_1 … #define mmDCORE0_TPC0_QM_PQC_HBW_BASE_LO_2 … #define mmDCORE0_TPC0_QM_PQC_HBW_BASE_LO_3 … #define mmDCORE0_TPC0_QM_PQC_HBW_BASE_HI_0 … #define mmDCORE0_TPC0_QM_PQC_HBW_BASE_HI_1 … #define mmDCORE0_TPC0_QM_PQC_HBW_BASE_HI_2 … #define mmDCORE0_TPC0_QM_PQC_HBW_BASE_HI_3 … #define mmDCORE0_TPC0_QM_PQC_SIZE_0 … #define mmDCORE0_TPC0_QM_PQC_SIZE_1 … #define mmDCORE0_TPC0_QM_PQC_SIZE_2 … #define mmDCORE0_TPC0_QM_PQC_SIZE_3 … #define mmDCORE0_TPC0_QM_PQC_PI_0 … #define mmDCORE0_TPC0_QM_PQC_PI_1 … #define mmDCORE0_TPC0_QM_PQC_PI_2 … #define mmDCORE0_TPC0_QM_PQC_PI_3 … #define mmDCORE0_TPC0_QM_PQC_LBW_WDATA_0 … #define mmDCORE0_TPC0_QM_PQC_LBW_WDATA_1 … #define mmDCORE0_TPC0_QM_PQC_LBW_WDATA_2 … #define mmDCORE0_TPC0_QM_PQC_LBW_WDATA_3 … #define mmDCORE0_TPC0_QM_PQC_LBW_BASE_LO_0 … #define mmDCORE0_TPC0_QM_PQC_LBW_BASE_LO_1 … #define mmDCORE0_TPC0_QM_PQC_LBW_BASE_LO_2 … #define mmDCORE0_TPC0_QM_PQC_LBW_BASE_LO_3 … #define mmDCORE0_TPC0_QM_PQC_LBW_BASE_HI_0 … #define mmDCORE0_TPC0_QM_PQC_LBW_BASE_HI_1 … #define mmDCORE0_TPC0_QM_PQC_LBW_BASE_HI_2 … #define mmDCORE0_TPC0_QM_PQC_LBW_BASE_HI_3 … #define mmDCORE0_TPC0_QM_PQC_CFG … #define mmDCORE0_TPC0_QM_PQC_SECURE_PUSH_IND … #define mmDCORE0_TPC0_QM_ARB_MASK … #define mmDCORE0_TPC0_QM_ARB_CFG_0 … #define mmDCORE0_TPC0_QM_ARB_CHOICE_Q_PUSH … #define mmDCORE0_TPC0_QM_ARB_WRR_WEIGHT_0 … #define mmDCORE0_TPC0_QM_ARB_WRR_WEIGHT_1 … #define mmDCORE0_TPC0_QM_ARB_WRR_WEIGHT_2 … #define mmDCORE0_TPC0_QM_ARB_WRR_WEIGHT_3 … #define mmDCORE0_TPC0_QM_ARB_CFG_1 … #define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_0 … #define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_1 … #define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_2 … #define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_3 … #define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_4 … #define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_5 … #define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_6 … #define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_7 … #define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_8 … #define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_9 … #define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_10 … #define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_11 … #define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_12 … #define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_13 … #define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_14 … #define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_15 … #define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_16 … #define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_17 … #define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_18 … #define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_19 … #define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_20 … #define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_21 … #define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_22 … #define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_23 … #define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_24 … #define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_25 … #define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_26 … #define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_27 … #define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_28 … #define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_29 … #define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_30 … #define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_31 … #define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_32 … #define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_33 … #define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_34 … #define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_35 … #define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_36 … #define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_37 … #define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_38 … #define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_39 … #define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_40 … #define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_41 … #define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_42 … #define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_43 … #define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_44 … #define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_45 … #define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_46 … #define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_47 … #define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_48 … #define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_49 … #define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_50 … #define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_51 … #define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_52 … #define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_53 … #define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_54 … #define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_55 … #define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_56 … #define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_57 … #define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_58 … #define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_59 … #define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_60 … #define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_61 … #define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_62 … #define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_63 … #define mmDCORE0_TPC0_QM_ARB_MST_CRED_INC … #define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_0 … #define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_1 … #define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_2 … #define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_3 … #define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_4 … #define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_5 … #define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_6 … #define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_7 … #define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_8 … #define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_9 … #define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_10 … #define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_11 … #define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_12 … #define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_13 … #define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_14 … #define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_15 … #define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_16 … #define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_17 … #define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_18 … #define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_19 … #define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_20 … #define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_21 … #define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_22 … #define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_23 … #define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_24 … #define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_25 … #define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_26 … #define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_27 … #define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_28 … #define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_29 … #define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_30 … #define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_31 … #define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_32 … #define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_33 … #define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_34 … #define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_35 … #define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_36 … #define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_37 … #define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_38 … #define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_39 … #define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_40 … #define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_41 … #define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_42 … #define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_43 … #define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_44 … #define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_45 … #define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_46 … #define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_47 … #define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_48 … #define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_49 … #define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_50 … #define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_51 … #define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_52 … #define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_53 … #define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_54 … #define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_55 … #define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_56 … #define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_57 … #define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_58 … #define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_59 … #define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_60 … #define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_61 … #define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_62 … #define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_63 … #define mmDCORE0_TPC0_QM_ARB_SLV_MASTER_INC_CRED_OFST … #define mmDCORE0_TPC0_QM_ARB_MST_SLAVE_EN … #define mmDCORE0_TPC0_QM_ARB_MST_SLAVE_EN_1 … #define mmDCORE0_TPC0_QM_ARB_SLV_CHOICE_WDT … #define mmDCORE0_TPC0_QM_ARB_SLV_ID … #define mmDCORE0_TPC0_QM_ARB_MST_QUIET_PER … #define mmDCORE0_TPC0_QM_ARB_MSG_MAX_INFLIGHT … #define mmDCORE0_TPC0_QM_ARB_BASE_LO … #define mmDCORE0_TPC0_QM_ARB_BASE_HI … #define mmDCORE0_TPC0_QM_ARB_STATE_STS … #define mmDCORE0_TPC0_QM_ARB_CHOICE_FULLNESS_STS … #define mmDCORE0_TPC0_QM_ARB_MSG_STS … #define mmDCORE0_TPC0_QM_ARB_SLV_CHOICE_Q_HEAD … #define mmDCORE0_TPC0_QM_ARB_ERR_CAUSE … #define mmDCORE0_TPC0_QM_ARB_ERR_MSG_EN … #define mmDCORE0_TPC0_QM_ARB_ERR_STS_DRP … #define mmDCORE0_TPC0_QM_ARB_MST_CRED_STS … #define mmDCORE0_TPC0_QM_ARB_MST_CRED_STS_1 … #define mmDCORE0_TPC0_QM_CSMR_STRICT_PRIO_CFG … #define mmDCORE0_TPC0_QM_ARC_CQ_CFG0 … #define mmDCORE0_TPC0_QM_ARC_CQ_CFG1 … #define mmDCORE0_TPC0_QM_ARC_CQ_PTR_LO … #define mmDCORE0_TPC0_QM_ARC_CQ_PTR_HI … #define mmDCORE0_TPC0_QM_ARC_CQ_TSIZE … #define mmDCORE0_TPC0_QM_ARC_CQ_CTL … #define mmDCORE0_TPC0_QM_ARC_CQ_IFIFO_STS … #define mmDCORE0_TPC0_QM_ARC_CQ_STS0 … #define mmDCORE0_TPC0_QM_ARC_CQ_STS1 … #define mmDCORE0_TPC0_QM_ARC_CQ_TSIZE_STS … #define mmDCORE0_TPC0_QM_ARC_CQ_PTR_LO_STS … #define mmDCORE0_TPC0_QM_ARC_CQ_PTR_HI_STS … #define mmDCORE0_TPC0_QM_CP_WR_ARC_ADDR_HI … #define mmDCORE0_TPC0_QM_CP_WR_ARC_ADDR_LO … #define mmDCORE0_TPC0_QM_ARC_CQ_IFIFO_MSG_BASE_HI … #define mmDCORE0_TPC0_QM_ARC_CQ_IFIFO_MSG_BASE_LO … #define mmDCORE0_TPC0_QM_ARC_CQ_CTL_MSG_BASE_HI … #define mmDCORE0_TPC0_QM_ARC_CQ_CTL_MSG_BASE_LO … #define mmDCORE0_TPC0_QM_CQ_IFIFO_MSG_BASE_HI … #define mmDCORE0_TPC0_QM_CQ_IFIFO_MSG_BASE_LO … #define mmDCORE0_TPC0_QM_CQ_CTL_MSG_BASE_HI … #define mmDCORE0_TPC0_QM_CQ_CTL_MSG_BASE_LO … #define mmDCORE0_TPC0_QM_ADDR_OVRD … #define mmDCORE0_TPC0_QM_CQ_IFIFO_CI_0 … #define mmDCORE0_TPC0_QM_CQ_IFIFO_CI_1 … #define mmDCORE0_TPC0_QM_CQ_IFIFO_CI_2 … #define mmDCORE0_TPC0_QM_CQ_IFIFO_CI_3 … #define mmDCORE0_TPC0_QM_CQ_IFIFO_CI_4 … #define mmDCORE0_TPC0_QM_ARC_CQ_IFIFO_CI … #define mmDCORE0_TPC0_QM_CQ_CTL_CI_0 … #define mmDCORE0_TPC0_QM_CQ_CTL_CI_1 … #define mmDCORE0_TPC0_QM_CQ_CTL_CI_2 … #define mmDCORE0_TPC0_QM_CQ_CTL_CI_3 … #define mmDCORE0_TPC0_QM_CQ_CTL_CI_4 … #define mmDCORE0_TPC0_QM_ARC_CQ_CTL_CI … #define mmDCORE0_TPC0_QM_CP_CFG … #define mmDCORE0_TPC0_QM_CP_EXT_SWITCH … #define mmDCORE0_TPC0_QM_CP_SWITCH_WD_SET … #define mmDCORE0_TPC0_QM_CP_SWITCH_WD … #define mmDCORE0_TPC0_QM_ARC_LB_ADDR_BASE_LO … #define mmDCORE0_TPC0_QM_ARC_LB_ADDR_BASE_HI … #define mmDCORE0_TPC0_QM_ENGINE_BASE_ADDR_HI … #define mmDCORE0_TPC0_QM_ENGINE_BASE_ADDR_LO … #define mmDCORE0_TPC0_QM_ENGINE_ADDR_RANGE_SIZE … #define mmDCORE0_TPC0_QM_QM_ARC_AUX_BASE_ADDR_HI … #define mmDCORE0_TPC0_QM_QM_ARC_AUX_BASE_ADDR_LO … #define mmDCORE0_TPC0_QM_QM_BASE_ADDR_HI … #define mmDCORE0_TPC0_QM_QM_BASE_ADDR_LO … #define mmDCORE0_TPC0_QM_ARC_PQC_SECURE_PUSH_IND … #define mmDCORE0_TPC0_QM_PQC_STS_0_0 … #define mmDCORE0_TPC0_QM_PQC_STS_0_1 … #define mmDCORE0_TPC0_QM_PQC_STS_0_2 … #define mmDCORE0_TPC0_QM_PQC_STS_0_3 … #define mmDCORE0_TPC0_QM_PQC_STS_1_0 … #define mmDCORE0_TPC0_QM_PQC_STS_1_1 … #define mmDCORE0_TPC0_QM_PQC_STS_1_2 … #define mmDCORE0_TPC0_QM_PQC_STS_1_3 … #define mmDCORE0_TPC0_QM_SEI_STATUS … #define mmDCORE0_TPC0_QM_SEI_MASK … #define mmDCORE0_TPC0_QM_GLBL_ERR_ADDR_LO … #define mmDCORE0_TPC0_QM_GLBL_ERR_ADDR_HI … #define mmDCORE0_TPC0_QM_GLBL_ERR_WDATA … #define mmDCORE0_TPC0_QM_L2H_MASK_LO … #define mmDCORE0_TPC0_QM_L2H_MASK_HI … #define mmDCORE0_TPC0_QM_L2H_CMPR_LO … #define mmDCORE0_TPC0_QM_L2H_CMPR_HI … #define mmDCORE0_TPC0_QM_LOCAL_RANGE_BASE … #define mmDCORE0_TPC0_QM_LOCAL_RANGE_SIZE … #define mmDCORE0_TPC0_QM_HBW_RD_RATE_LIM_CFG_1 … #define mmDCORE0_TPC0_QM_LBW_WR_RATE_LIM_CFG_0 … #define mmDCORE0_TPC0_QM_LBW_WR_RATE_LIM_CFG_1 … #define mmDCORE0_TPC0_QM_HBW_RD_RATE_LIM_CFG_0 … #define mmDCORE0_TPC0_QM_IND_GW_APB_CFG … #define mmDCORE0_TPC0_QM_IND_GW_APB_WDATA … #define mmDCORE0_TPC0_QM_IND_GW_APB_RDATA … #define mmDCORE0_TPC0_QM_IND_GW_APB_STATUS … #define mmDCORE0_TPC0_QM_PERF_CNT_FREE_LO … #define mmDCORE0_TPC0_QM_PERF_CNT_FREE_HI … #define mmDCORE0_TPC0_QM_PERF_CNT_IDLE_LO … #define mmDCORE0_TPC0_QM_PERF_CNT_IDLE_HI … #define mmDCORE0_TPC0_QM_PERF_CNT_CFG … #endif /* ASIC_REG_DCORE0_TPC0_QM_REGS_H_ */
Codebase Browser
linux