/* SPDX-License-Identifier: GPL-2.0 * * Copyright 2016-2020 HabanaLabs, Ltd. * All Rights Reserved. * */ /************************************ ** This is an auto-generated file ** ** DO NOT EDIT BELOW ** ************************************/ #ifndef ASIC_REG_DCORE0_TPC0_QM_ARC_AUX_REGS_H_ #define ASIC_REG_DCORE0_TPC0_QM_ARC_AUX_REGS_H_ /* ***************************************** * DCORE0_TPC0_QM_ARC_AUX * (Prototype: QMAN_ARC_AUX) ***************************************** */ #define mmDCORE0_TPC0_QM_ARC_AUX_RUN_HALT_REQ … #define mmDCORE0_TPC0_QM_ARC_AUX_RUN_HALT_ACK … #define mmDCORE0_TPC0_QM_ARC_AUX_RST_VEC_ADDR … #define mmDCORE0_TPC0_QM_ARC_AUX_DBG_MODE … #define mmDCORE0_TPC0_QM_ARC_AUX_CLUSTER_NUM … #define mmDCORE0_TPC0_QM_ARC_AUX_ARC_NUM … #define mmDCORE0_TPC0_QM_ARC_AUX_WAKE_UP_EVENT … #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_SYS_ADDR_BASE … #define mmDCORE0_TPC0_QM_ARC_AUX_CTI_AP_STS … #define mmDCORE0_TPC0_QM_ARC_AUX_CTI_CFG_MUX_SEL … #define mmDCORE0_TPC0_QM_ARC_AUX_ARC_RST … #define mmDCORE0_TPC0_QM_ARC_AUX_ARC_RST_REQ … #define mmDCORE0_TPC0_QM_ARC_AUX_SRAM_LSB_ADDR … #define mmDCORE0_TPC0_QM_ARC_AUX_SRAM_MSB_ADDR … #define mmDCORE0_TPC0_QM_ARC_AUX_PCIE_LSB_ADDR … #define mmDCORE0_TPC0_QM_ARC_AUX_PCIE_MSB_ADDR … #define mmDCORE0_TPC0_QM_ARC_AUX_CFG_LSB_ADDR … #define mmDCORE0_TPC0_QM_ARC_AUX_CFG_MSB_ADDR … #define mmDCORE0_TPC0_QM_ARC_AUX_HBM0_LSB_ADDR … #define mmDCORE0_TPC0_QM_ARC_AUX_HBM0_MSB_ADDR … #define mmDCORE0_TPC0_QM_ARC_AUX_HBM1_LSB_ADDR … #define mmDCORE0_TPC0_QM_ARC_AUX_HBM1_MSB_ADDR … #define mmDCORE0_TPC0_QM_ARC_AUX_HBM2_LSB_ADDR … #define mmDCORE0_TPC0_QM_ARC_AUX_HBM2_MSB_ADDR … #define mmDCORE0_TPC0_QM_ARC_AUX_HBM3_LSB_ADDR … #define mmDCORE0_TPC0_QM_ARC_AUX_HBM3_MSB_ADDR … #define mmDCORE0_TPC0_QM_ARC_AUX_HBM0_OFFSET … #define mmDCORE0_TPC0_QM_ARC_AUX_HBM1_OFFSET … #define mmDCORE0_TPC0_QM_ARC_AUX_HBM2_OFFSET … #define mmDCORE0_TPC0_QM_ARC_AUX_HBM3_OFFSET … #define mmDCORE0_TPC0_QM_ARC_AUX_GENERAL_PURPOSE_LSB_ADDR_0 … #define mmDCORE0_TPC0_QM_ARC_AUX_GENERAL_PURPOSE_LSB_ADDR_1 … #define mmDCORE0_TPC0_QM_ARC_AUX_GENERAL_PURPOSE_LSB_ADDR_2 … #define mmDCORE0_TPC0_QM_ARC_AUX_GENERAL_PURPOSE_LSB_ADDR_3 … #define mmDCORE0_TPC0_QM_ARC_AUX_GENERAL_PURPOSE_LSB_ADDR_4 … #define mmDCORE0_TPC0_QM_ARC_AUX_GENERAL_PURPOSE_LSB_ADDR_5 … #define mmDCORE0_TPC0_QM_ARC_AUX_GENERAL_PURPOSE_LSB_ADDR_6 … #define mmDCORE0_TPC0_QM_ARC_AUX_GENERAL_PURPOSE_MSB_ADDR_0 … #define mmDCORE0_TPC0_QM_ARC_AUX_GENERAL_PURPOSE_MSB_ADDR_1 … #define mmDCORE0_TPC0_QM_ARC_AUX_GENERAL_PURPOSE_MSB_ADDR_2 … #define mmDCORE0_TPC0_QM_ARC_AUX_GENERAL_PURPOSE_MSB_ADDR_3 … #define mmDCORE0_TPC0_QM_ARC_AUX_GENERAL_PURPOSE_MSB_ADDR_4 … #define mmDCORE0_TPC0_QM_ARC_AUX_GENERAL_PURPOSE_MSB_ADDR_5 … #define mmDCORE0_TPC0_QM_ARC_AUX_GENERAL_PURPOSE_MSB_ADDR_6 … #define mmDCORE0_TPC0_QM_ARC_AUX_ARC_CBU_AWCACHE_OVR … #define mmDCORE0_TPC0_QM_ARC_AUX_ARC_LBU_AWCACHE_OVR … #define mmDCORE0_TPC0_QM_ARC_AUX_CONTEXT_ID_0 … #define mmDCORE0_TPC0_QM_ARC_AUX_CONTEXT_ID_1 … #define mmDCORE0_TPC0_QM_ARC_AUX_CONTEXT_ID_2 … #define mmDCORE0_TPC0_QM_ARC_AUX_CONTEXT_ID_3 … #define mmDCORE0_TPC0_QM_ARC_AUX_CONTEXT_ID_4 … #define mmDCORE0_TPC0_QM_ARC_AUX_CONTEXT_ID_5 … #define mmDCORE0_TPC0_QM_ARC_AUX_CONTEXT_ID_6 … #define mmDCORE0_TPC0_QM_ARC_AUX_CONTEXT_ID_7 … #define mmDCORE0_TPC0_QM_ARC_AUX_CID_OFFSET_0 … #define mmDCORE0_TPC0_QM_ARC_AUX_CID_OFFSET_1 … #define mmDCORE0_TPC0_QM_ARC_AUX_CID_OFFSET_2 … #define mmDCORE0_TPC0_QM_ARC_AUX_CID_OFFSET_3 … #define mmDCORE0_TPC0_QM_ARC_AUX_CID_OFFSET_4 … #define mmDCORE0_TPC0_QM_ARC_AUX_CID_OFFSET_5 … #define mmDCORE0_TPC0_QM_ARC_AUX_CID_OFFSET_6 … #define mmDCORE0_TPC0_QM_ARC_AUX_CID_OFFSET_7 … #define mmDCORE0_TPC0_QM_ARC_AUX_SW_INTR_0 … #define mmDCORE0_TPC0_QM_ARC_AUX_SW_INTR_1 … #define mmDCORE0_TPC0_QM_ARC_AUX_SW_INTR_2 … #define mmDCORE0_TPC0_QM_ARC_AUX_SW_INTR_3 … #define mmDCORE0_TPC0_QM_ARC_AUX_SW_INTR_4 … #define mmDCORE0_TPC0_QM_ARC_AUX_SW_INTR_5 … #define mmDCORE0_TPC0_QM_ARC_AUX_SW_INTR_6 … #define mmDCORE0_TPC0_QM_ARC_AUX_SW_INTR_7 … #define mmDCORE0_TPC0_QM_ARC_AUX_SW_INTR_8 … #define mmDCORE0_TPC0_QM_ARC_AUX_SW_INTR_9 … #define mmDCORE0_TPC0_QM_ARC_AUX_SW_INTR_10 … #define mmDCORE0_TPC0_QM_ARC_AUX_SW_INTR_11 … #define mmDCORE0_TPC0_QM_ARC_AUX_SW_INTR_12 … #define mmDCORE0_TPC0_QM_ARC_AUX_SW_INTR_13 … #define mmDCORE0_TPC0_QM_ARC_AUX_SW_INTR_14 … #define mmDCORE0_TPC0_QM_ARC_AUX_SW_INTR_15 … #define mmDCORE0_TPC0_QM_ARC_AUX_IRQ_INTR_MASK_0 … #define mmDCORE0_TPC0_QM_ARC_AUX_IRQ_INTR_MASK_1 … #define mmDCORE0_TPC0_QM_ARC_AUX_ARC_SEI_INTR_STS … #define mmDCORE0_TPC0_QM_ARC_AUX_ARC_SEI_INTR_CLR … #define mmDCORE0_TPC0_QM_ARC_AUX_ARC_SEI_INTR_MASK … #define mmDCORE0_TPC0_QM_ARC_AUX_ARC_EXCPTN_CAUSE … #define mmDCORE0_TPC0_QM_ARC_AUX_SEI_INTR_HALT_EN … #define mmDCORE0_TPC0_QM_ARC_AUX_ARC_SEI_INTR_HALT_MASK … #define mmDCORE0_TPC0_QM_ARC_AUX_QMAN_SEI_INTR_HALT_MASK … #define mmDCORE0_TPC0_QM_ARC_AUX_ARC_REI_INTR_STS … #define mmDCORE0_TPC0_QM_ARC_AUX_ARC_REI_INTR_CLR … #define mmDCORE0_TPC0_QM_ARC_AUX_ARC_REI_INTR_MASK … #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_ECC_ERR_ADDR … #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_ECC_SYNDROME … #define mmDCORE0_TPC0_QM_ARC_AUX_I_CACHE_ECC_ERR_ADDR … #define mmDCORE0_TPC0_QM_ARC_AUX_I_CACHE_ECC_SYNDROME … #define mmDCORE0_TPC0_QM_ARC_AUX_D_CACHE_ECC_ERR_ADDR … #define mmDCORE0_TPC0_QM_ARC_AUX_D_CACHE_ECC_SYNDROME … #define mmDCORE0_TPC0_QM_ARC_AUX_LBW_TRMINATE_AWADDR_ERR … #define mmDCORE0_TPC0_QM_ARC_AUX_LBW_TRMINATE_ARADDR_ERR … #define mmDCORE0_TPC0_QM_ARC_AUX_CFG_LBW_TERMINATE_BRESP … #define mmDCORE0_TPC0_QM_ARC_AUX_CFG_LBW_TERMINATE_RRESP … #define mmDCORE0_TPC0_QM_ARC_AUX_CFG_LBW_TERMINATE_AXLEN … #define mmDCORE0_TPC0_QM_ARC_AUX_CFG_LBW_TERMINATE_AXSIZE … #define mmDCORE0_TPC0_QM_ARC_AUX_SCRATCHPAD_0 … #define mmDCORE0_TPC0_QM_ARC_AUX_SCRATCHPAD_1 … #define mmDCORE0_TPC0_QM_ARC_AUX_SCRATCHPAD_2 … #define mmDCORE0_TPC0_QM_ARC_AUX_SCRATCHPAD_3 … #define mmDCORE0_TPC0_QM_ARC_AUX_SCRATCHPAD_4 … #define mmDCORE0_TPC0_QM_ARC_AUX_SCRATCHPAD_5 … #define mmDCORE0_TPC0_QM_ARC_AUX_SCRATCHPAD_6 … #define mmDCORE0_TPC0_QM_ARC_AUX_SCRATCHPAD_7 … #define mmDCORE0_TPC0_QM_ARC_AUX_TOTAL_CBU_WR_CNT … #define mmDCORE0_TPC0_QM_ARC_AUX_INFLIGHT_CBU_WR_CNT … #define mmDCORE0_TPC0_QM_ARC_AUX_TOTAL_CBU_RD_CNT … #define mmDCORE0_TPC0_QM_ARC_AUX_INFLIGHT_CBU_RD_CNT … #define mmDCORE0_TPC0_QM_ARC_AUX_TOTAL_LBU_WR_CNT … #define mmDCORE0_TPC0_QM_ARC_AUX_INFLIGHT_LBU_WR_CNT … #define mmDCORE0_TPC0_QM_ARC_AUX_TOTAL_LBU_RD_CNT … #define mmDCORE0_TPC0_QM_ARC_AUX_INFLIGHT_LBU_RD_CNT … #define mmDCORE0_TPC0_QM_ARC_AUX_CBU_ARUSER_OVR … #define mmDCORE0_TPC0_QM_ARC_AUX_CBU_ARUSER_OVR_EN … #define mmDCORE0_TPC0_QM_ARC_AUX_CBU_AWUSER_OVR … #define mmDCORE0_TPC0_QM_ARC_AUX_CBU_AWUSER_OVR_EN … #define mmDCORE0_TPC0_QM_ARC_AUX_CBU_ARUSER_MSB_OVR … #define mmDCORE0_TPC0_QM_ARC_AUX_CBU_ARUSER_MSB_OVR_EN … #define mmDCORE0_TPC0_QM_ARC_AUX_CBU_AWUSER_MSB_OVR … #define mmDCORE0_TPC0_QM_ARC_AUX_CBU_AWUSER_MSB_OVR_EN … #define mmDCORE0_TPC0_QM_ARC_AUX_CBU_AXCACHE_OVR … #define mmDCORE0_TPC0_QM_ARC_AUX_CBU_LOCK_OVR … #define mmDCORE0_TPC0_QM_ARC_AUX_CBU_PROT_OVR … #define mmDCORE0_TPC0_QM_ARC_AUX_CBU_MAX_OUTSTANDING … #define mmDCORE0_TPC0_QM_ARC_AUX_CBU_EARLY_BRESP_EN … #define mmDCORE0_TPC0_QM_ARC_AUX_CBU_FORCE_RSP_OK … #define mmDCORE0_TPC0_QM_ARC_AUX_CBU_NO_WR_INFLIGHT … #define mmDCORE0_TPC0_QM_ARC_AUX_CBU_SEI_INTR_ID … #define mmDCORE0_TPC0_QM_ARC_AUX_LBU_ARUSER_OVR … #define mmDCORE0_TPC0_QM_ARC_AUX_LBU_ARUSER_OVR_EN … #define mmDCORE0_TPC0_QM_ARC_AUX_LBU_AWUSER_OVR … #define mmDCORE0_TPC0_QM_ARC_AUX_LBU_AWUSER_OVR_EN … #define mmDCORE0_TPC0_QM_ARC_AUX_LBU_AXCACHE_OVR … #define mmDCORE0_TPC0_QM_ARC_AUX_LBU_LOCK_OVR … #define mmDCORE0_TPC0_QM_ARC_AUX_LBU_PROT_OVR … #define mmDCORE0_TPC0_QM_ARC_AUX_LBU_MAX_OUTSTANDING … #define mmDCORE0_TPC0_QM_ARC_AUX_LBU_EARLY_BRESP_EN … #define mmDCORE0_TPC0_QM_ARC_AUX_LBU_FORCE_RSP_OK … #define mmDCORE0_TPC0_QM_ARC_AUX_LBU_NO_WR_INFLIGHT … #define mmDCORE0_TPC0_QM_ARC_AUX_LBU_SEI_INTR_ID … #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_BASE_ADDR_0 … #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_BASE_ADDR_1 … #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_BASE_ADDR_2 … #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_BASE_ADDR_3 … #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_BASE_ADDR_4 … #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_BASE_ADDR_5 … #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_BASE_ADDR_6 … #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_BASE_ADDR_7 … #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_SIZE_0 … #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_SIZE_1 … #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_SIZE_2 … #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_SIZE_3 … #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_SIZE_4 … #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_SIZE_5 … #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_SIZE_6 … #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_SIZE_7 … #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_PI_0 … #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_PI_1 … #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_PI_2 … #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_PI_3 … #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_PI_4 … #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_PI_5 … #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_PI_6 … #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_PI_7 … #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_CI_0 … #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_CI_1 … #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_CI_2 … #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_CI_3 … #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_CI_4 … #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_CI_5 … #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_CI_6 … #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_CI_7 … #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_PUSH_REG_0 … #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_PUSH_REG_1 … #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_PUSH_REG_2 … #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_PUSH_REG_3 … #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_PUSH_REG_4 … #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_PUSH_REG_5 … #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_PUSH_REG_6 … #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_PUSH_REG_7 … #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_MAX_OCCUPANCY_0 … #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_MAX_OCCUPANCY_1 … #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_MAX_OCCUPANCY_2 … #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_MAX_OCCUPANCY_3 … #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_MAX_OCCUPANCY_4 … #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_MAX_OCCUPANCY_5 … #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_MAX_OCCUPANCY_6 … #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_MAX_OCCUPANCY_7 … #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_VALID_ENTRIES_0 … #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_VALID_ENTRIES_1 … #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_VALID_ENTRIES_2 … #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_VALID_ENTRIES_3 … #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_VALID_ENTRIES_4 … #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_VALID_ENTRIES_5 … #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_VALID_ENTRIES_6 … #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_VALID_ENTRIES_7 … #define mmDCORE0_TPC0_QM_ARC_AUX_GENERAL_Q_VLD_ENTRY_MASK … #define mmDCORE0_TPC0_QM_ARC_AUX_NIC_Q_VLD_ENTRY_MASK … #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_DROP_EN … #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_WARN_MSG … #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_ALERT_MSG … #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_GEN_AXI_AWPROT … #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_GEN_AXI_AWUSER … #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_GEN_AXI_AWBURST … #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_GEN_AXI_AWLOCK … #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_GEN_AXI_AWCACHE … #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_WRR_ARB_WEIGHT … #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_Q_PUSH_FIFO_FULL_CFG … #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_Q_PUSH_FIFO_CNT … #define mmDCORE0_TPC0_QM_ARC_AUX_QMAN_CQ_IFIFO_SHADOW_CI … #define mmDCORE0_TPC0_QM_ARC_AUX_QMAN_ARC_CQ_IFIFO_SHADOW_CI … #define mmDCORE0_TPC0_QM_ARC_AUX_QMAN_CQ_SHADOW_CI … #define mmDCORE0_TPC0_QM_ARC_AUX_QMAN_ARC_CQ_SHADOW_CI … #define mmDCORE0_TPC0_QM_ARC_AUX_AUX2APB_PROT … #define mmDCORE0_TPC0_QM_ARC_AUX_LBW_FORK_WIN_EN … #define mmDCORE0_TPC0_QM_ARC_AUX_QMAN_LBW_FORK_BASE_ADDR0 … #define mmDCORE0_TPC0_QM_ARC_AUX_QMAN_LBW_FORK_ADDR_MASK0 … #define mmDCORE0_TPC0_QM_ARC_AUX_QMAN_LBW_FORK_BASE_ADDR1 … #define mmDCORE0_TPC0_QM_ARC_AUX_QMAN_LBW_FORK_ADDR_MASK1 … #define mmDCORE0_TPC0_QM_ARC_AUX_FARM_LBW_FORK_BASE_ADDR0 … #define mmDCORE0_TPC0_QM_ARC_AUX_FARM_LBW_FORK_ADDR_MASK0 … #define mmDCORE0_TPC0_QM_ARC_AUX_FARM_LBW_FORK_BASE_ADDR1 … #define mmDCORE0_TPC0_QM_ARC_AUX_FARM_LBW_FORK_ADDR_MASK1 … #define mmDCORE0_TPC0_QM_ARC_AUX_LBW_APB_FORK_MAX_ADDR0 … #define mmDCORE0_TPC0_QM_ARC_AUX_LBW_APB_FORK_MAX_ADDR1 … #define mmDCORE0_TPC0_QM_ARC_AUX_ARC_ACC_ENGS_LBW_FORK_MASK … #define mmDCORE0_TPC0_QM_ARC_AUX_ARC_DUP_ENG_LBW_FORK_ADDR … #define mmDCORE0_TPC0_QM_ARC_AUX_ARC_ACP_ENG_LBW_FORK_ADDR … #define mmDCORE0_TPC0_QM_ARC_AUX_ARC_ACC_ENGS_VIRTUAL_ADDR … #define mmDCORE0_TPC0_QM_ARC_AUX_CBU_FORK_WIN_EN … #define mmDCORE0_TPC0_QM_ARC_AUX_CBU_FORK_BASE_ADDR0_LSB … #define mmDCORE0_TPC0_QM_ARC_AUX_CBU_FORK_BASE_ADDR0_MSB … #define mmDCORE0_TPC0_QM_ARC_AUX_CBU_FORK_ADDR_MASK0_LSB … #define mmDCORE0_TPC0_QM_ARC_AUX_CBU_FORK_ADDR_MASK0_MSB … #define mmDCORE0_TPC0_QM_ARC_AUX_CBU_FORK_BASE_ADDR1_LSB … #define mmDCORE0_TPC0_QM_ARC_AUX_CBU_FORK_BASE_ADDR1_MSB … #define mmDCORE0_TPC0_QM_ARC_AUX_CBU_FORK_ADDR_MASK1_LSB … #define mmDCORE0_TPC0_QM_ARC_AUX_CBU_FORK_ADDR_MASK1_MSB … #define mmDCORE0_TPC0_QM_ARC_AUX_CBU_FORK_BASE_ADDR2_LSB … #define mmDCORE0_TPC0_QM_ARC_AUX_CBU_FORK_BASE_ADDR2_MSB … #define mmDCORE0_TPC0_QM_ARC_AUX_CBU_FORK_ADDR_MASK2_LSB … #define mmDCORE0_TPC0_QM_ARC_AUX_CBU_FORK_ADDR_MASK2_MSB … #define mmDCORE0_TPC0_QM_ARC_AUX_CBU_FORK_BASE_ADDR3_LSB … #define mmDCORE0_TPC0_QM_ARC_AUX_CBU_FORK_BASE_ADDR3_MSB … #define mmDCORE0_TPC0_QM_ARC_AUX_CBU_FORK_ADDR_MASK3_LSB … #define mmDCORE0_TPC0_QM_ARC_AUX_CBU_FORK_ADDR_MASK3_MSB … #define mmDCORE0_TPC0_QM_ARC_AUX_CBU_TRMINATE_ARADDR_LSB … #define mmDCORE0_TPC0_QM_ARC_AUX_CBU_TRMINATE_ARADDR_MSB … #define mmDCORE0_TPC0_QM_ARC_AUX_CFG_CBU_TERMINATE_BRESP … #define mmDCORE0_TPC0_QM_ARC_AUX_CFG_CBU_TERMINATE_RRESP … #define mmDCORE0_TPC0_QM_ARC_AUX_ARC_REGION_CFG_0 … #define mmDCORE0_TPC0_QM_ARC_AUX_ARC_REGION_CFG_1 … #define mmDCORE0_TPC0_QM_ARC_AUX_ARC_REGION_CFG_2 … #define mmDCORE0_TPC0_QM_ARC_AUX_ARC_REGION_CFG_3 … #define mmDCORE0_TPC0_QM_ARC_AUX_ARC_REGION_CFG_4 … #define mmDCORE0_TPC0_QM_ARC_AUX_ARC_REGION_CFG_5 … #define mmDCORE0_TPC0_QM_ARC_AUX_ARC_REGION_CFG_6 … #define mmDCORE0_TPC0_QM_ARC_AUX_ARC_REGION_CFG_7 … #define mmDCORE0_TPC0_QM_ARC_AUX_ARC_REGION_CFG_8 … #define mmDCORE0_TPC0_QM_ARC_AUX_ARC_REGION_CFG_9 … #define mmDCORE0_TPC0_QM_ARC_AUX_ARC_REGION_CFG_10 … #define mmDCORE0_TPC0_QM_ARC_AUX_ARC_REGION_CFG_11 … #define mmDCORE0_TPC0_QM_ARC_AUX_ARC_REGION_CFG_12 … #define mmDCORE0_TPC0_QM_ARC_AUX_ARC_REGION_CFG_13 … #define mmDCORE0_TPC0_QM_ARC_AUX_ARC_REGION_CFG_14 … #define mmDCORE0_TPC0_QM_ARC_AUX_ARC_REGION_CFG_15 … #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_TRMINATE_AWADDR_ERR … #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_TRMINATE_ARADDR_ERR … #define mmDCORE0_TPC0_QM_ARC_AUX_CFG_DCCM_TERMINATE_BRESP … #define mmDCORE0_TPC0_QM_ARC_AUX_CFG_DCCM_TERMINATE_RRESP … #define mmDCORE0_TPC0_QM_ARC_AUX_CFG_DCCM_TERMINATE_EN … #define mmDCORE0_TPC0_QM_ARC_AUX_CFG_DCCM_SECURE_REGION … #define mmDCORE0_TPC0_QM_ARC_AUX_ARC_AXI_ORDERING_WR_IF_CNT … #define mmDCORE0_TPC0_QM_ARC_AUX_ARC_AXI_ORDERING_CTL … #define mmDCORE0_TPC0_QM_ARC_AUX_ARC_AXI_ORDERING_ADDR_MSK … #define mmDCORE0_TPC0_QM_ARC_AUX_ARC_AXI_ORDERING_ADDR … #define mmDCORE0_TPC0_QM_ARC_AUX_ARC_ACC_ENGS_BUSER … #define mmDCORE0_TPC0_QM_ARC_AUX_MME_ARC_UPPER_DCCM_EN … #endif /* ASIC_REG_DCORE0_TPC0_QM_ARC_AUX_REGS_H_ */
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