/* SPDX-License-Identifier: GPL-2.0 * * Copyright 2016-2020 HabanaLabs, Ltd. * All Rights Reserved. * */ /************************************ ** This is an auto-generated file ** ** DO NOT EDIT BELOW ** ************************************/ #ifndef ASIC_REG_DCORE0_TPC0_CFG_REGS_H_ #define ASIC_REG_DCORE0_TPC0_CFG_REGS_H_ /* ***************************************** * DCORE0_TPC0_CFG * (Prototype: TPC) ***************************************** */ #define mmDCORE0_TPC0_CFG_TPC_COUNT … #define mmDCORE0_TPC0_CFG_TPC_ID … #define mmDCORE0_TPC0_CFG_STALL_ON_ERR … #define mmDCORE0_TPC0_CFG_CLK_EN … #define mmDCORE0_TPC0_CFG_IQ_RL_EN … #define mmDCORE0_TPC0_CFG_IQ_RL_SAT … #define mmDCORE0_TPC0_CFG_IQ_RL_RST_TOKEN … #define mmDCORE0_TPC0_CFG_IQ_RL_TIMEOUT … #define mmDCORE0_TPC0_CFG_TSB_CFG_MTRR_2_0 … #define mmDCORE0_TPC0_CFG_TSB_CFG_MTRR_2_1 … #define mmDCORE0_TPC0_CFG_TSB_CFG_MTRR_2_2 … #define mmDCORE0_TPC0_CFG_TSB_CFG_MTRR_2_3 … #define mmDCORE0_TPC0_CFG_IQ_LBW_CLK_EN … #define mmDCORE0_TPC0_CFG_TPC_LOCK_VALUE_0 … #define mmDCORE0_TPC0_CFG_TPC_LOCK_VALUE_1 … #define mmDCORE0_TPC0_CFG_TPC_LOCK_VALUE_2 … #define mmDCORE0_TPC0_CFG_TPC_LOCK_VALUE_3 … #define mmDCORE0_TPC0_CFG_TPC_LOCK_0 … #define mmDCORE0_TPC0_CFG_TPC_LOCK_1 … #define mmDCORE0_TPC0_CFG_TPC_LOCK_2 … #define mmDCORE0_TPC0_CFG_TPC_LOCK_3 … #define mmDCORE0_TPC0_CFG_CGU_SB … #define mmDCORE0_TPC0_CFG_CGU_CNT … #define mmDCORE0_TPC0_CFG_CGU_CPE_0 … #define mmDCORE0_TPC0_CFG_CGU_CPE_1 … #define mmDCORE0_TPC0_CFG_CGU_CPE_2 … #define mmDCORE0_TPC0_CFG_CGU_CPE_3 … #define mmDCORE0_TPC0_CFG_CGU_CPE_4 … #define mmDCORE0_TPC0_CFG_CGU_CPE_5 … #define mmDCORE0_TPC0_CFG_CGU_CPE_6 … #define mmDCORE0_TPC0_CFG_CGU_CPE_7 … #define mmDCORE0_TPC0_CFG_FP16_FTZ_IN … #define mmDCORE0_TPC0_CFG_DCACHE_CFG … #define mmDCORE0_TPC0_CFG_E2E_CRDT_TOP … #define mmDCORE0_TPC0_CFG_TPC_DCACHE_L0CD … #define mmDCORE0_TPC0_CFG_TPC_SB_L0CD … #define mmDCORE0_TPC0_CFG_CONV_ROUND_CSR … #define mmDCORE0_TPC0_CFG_TSB_OCCUPANCY … #define mmDCORE0_TPC0_CFG_ARB_QNT_HBW_WEIGHT … #define mmDCORE0_TPC0_CFG_ARB_QNT_LBW_WEIGHT … #define mmDCORE0_TPC0_CFG_ARB_CNT_HBW_WEIGHT … #define mmDCORE0_TPC0_CFG_ARB_CNT_LBW_WEIGHT … #define mmDCORE0_TPC0_CFG_LUT_FUNC32_BASE2_ADDR_LO … #define mmDCORE0_TPC0_CFG_LUT_FUNC32_BASE2_ADDR_HI … #define mmDCORE0_TPC0_CFG_LUT_FUNC64_BASE2_ADDR_LO … #define mmDCORE0_TPC0_CFG_LUT_FUNC64_BASE2_ADDR_HI … #define mmDCORE0_TPC0_CFG_LUT_FUNC128_BASE2_ADDR_LO … #define mmDCORE0_TPC0_CFG_LUT_FUNC128_BASE2_ADDR_HI … #define mmDCORE0_TPC0_CFG_LUT_FUNC256_BASE2_ADDR_LO … #define mmDCORE0_TPC0_CFG_LUT_FUNC256_BASE2_ADDR_HI … #define mmDCORE0_TPC0_CFG_SPE_LFSR_POLYNOM … #define mmDCORE0_TPC0_CFG_TSB_CFG_MTRR_GLBL … #define mmDCORE0_TPC0_CFG_TSB_CFG_MTRR_0 … #define mmDCORE0_TPC0_CFG_TSB_CFG_MTRR_1 … #define mmDCORE0_TPC0_CFG_TSB_CFG_MTRR_2 … #define mmDCORE0_TPC0_CFG_TSB_CFG_MTRR_3 … #define mmDCORE0_TPC0_CFG_TSB_CFG_MTRR_MASK_LO_0 … #define mmDCORE0_TPC0_CFG_TSB_CFG_MTRR_MASK_LO_1 … #define mmDCORE0_TPC0_CFG_TSB_CFG_MTRR_MASK_LO_2 … #define mmDCORE0_TPC0_CFG_TSB_CFG_MTRR_MASK_LO_3 … #define mmDCORE0_TPC0_CFG_TSB_CFG_MTRR_MASK_HI_0 … #define mmDCORE0_TPC0_CFG_TSB_CFG_MTRR_MASK_HI_1 … #define mmDCORE0_TPC0_CFG_TSB_CFG_MTRR_MASK_HI_2 … #define mmDCORE0_TPC0_CFG_TSB_CFG_MTRR_MASK_HI_3 … #define mmDCORE0_TPC0_CFG_FP8_143_BIAS … #define mmDCORE0_TPC0_CFG_ROUND_CSR … #define mmDCORE0_TPC0_CFG_HB_PROT … #define mmDCORE0_TPC0_CFG_LB_PROT … #define mmDCORE0_TPC0_CFG_SEMAPHORE … #define mmDCORE0_TPC0_CFG_VFLAGS … #define mmDCORE0_TPC0_CFG_SFLAGS … #define mmDCORE0_TPC0_CFG_LFSR_POLYNOM … #define mmDCORE0_TPC0_CFG_STATUS … #define mmDCORE0_TPC0_CFG_CFG_BASE_ADDRESS_HIGH … #define mmDCORE0_TPC0_CFG_CFG_SUBTRACT_VALUE … #define mmDCORE0_TPC0_CFG_SM_BASE_ADDRESS_HIGH … #define mmDCORE0_TPC0_CFG_TPC_CMD … #define mmDCORE0_TPC0_CFG_TPC_EXECUTE … #define mmDCORE0_TPC0_CFG_TPC_STALL … #define mmDCORE0_TPC0_CFG_ICACHE_BASE_ADDERESS_LOW … #define mmDCORE0_TPC0_CFG_ICACHE_BASE_ADDERESS_HIGH … #define mmDCORE0_TPC0_CFG_RD_RATE_LIMIT … #define mmDCORE0_TPC0_CFG_WR_RATE_LIMIT … #define mmDCORE0_TPC0_CFG_MSS_CONFIG … #define mmDCORE0_TPC0_CFG_TPC_INTR_CAUSE … #define mmDCORE0_TPC0_CFG_TPC_INTR_MASK … #define mmDCORE0_TPC0_CFG_WQ_CREDITS … #define mmDCORE0_TPC0_CFG_OPCODE_EXEC … #define mmDCORE0_TPC0_CFG_LUT_FUNC32_BASE_ADDR_LO … #define mmDCORE0_TPC0_CFG_LUT_FUNC32_BASE_ADDR_HI … #define mmDCORE0_TPC0_CFG_LUT_FUNC64_BASE_ADDR_LO … #define mmDCORE0_TPC0_CFG_LUT_FUNC64_BASE_ADDR_HI … #define mmDCORE0_TPC0_CFG_LUT_FUNC128_BASE_ADDR_LO … #define mmDCORE0_TPC0_CFG_LUT_FUNC128_BASE_ADDR_HI … #define mmDCORE0_TPC0_CFG_LUT_FUNC256_BASE_ADDR_LO … #define mmDCORE0_TPC0_CFG_LUT_FUNC256_BASE_ADDR_HI … #define mmDCORE0_TPC0_CFG_TSB_CFG_MAX_SIZE … #define mmDCORE0_TPC0_CFG_TSB_CFG … #define mmDCORE0_TPC0_CFG_TSB_INFLIGHT_CNTR … #define mmDCORE0_TPC0_CFG_WQ_INFLIGHT_CNTR … #define mmDCORE0_TPC0_CFG_WQ_LBW_TOTAL_CNTR … #define mmDCORE0_TPC0_CFG_WQ_HBW_TOTAL_CNTR … #define mmDCORE0_TPC0_CFG_IRQ_OCCOUPY_CNTR … #endif /* ASIC_REG_DCORE0_TPC0_CFG_REGS_H_ */
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