/* SPDX-License-Identifier: GPL-2.0 * * Copyright 2016-2020 HabanaLabs, Ltd. * All Rights Reserved. * */ /************************************ ** This is an auto-generated file ** ** DO NOT EDIT BELOW ** ************************************/ #ifndef ASIC_REG_DCORE0_TPC0_CFG_QM_REGS_H_ #define ASIC_REG_DCORE0_TPC0_CFG_QM_REGS_H_ /* ***************************************** * DCORE0_TPC0_CFG_QM * (Prototype: TPC_NON_TENSOR_DESCRIPTOR) ***************************************** */ #define mmDCORE0_TPC0_CFG_QM_KERNEL_BASE_ADDRESS_LOW … #define mmDCORE0_TPC0_CFG_QM_KERNEL_BASE_ADDRESS_HIGH … #define mmDCORE0_TPC0_CFG_QM_TID_BASE_DIM_0 … #define mmDCORE0_TPC0_CFG_QM_TID_SIZE_DIM_0 … #define mmDCORE0_TPC0_CFG_QM_TID_BASE_DIM_1 … #define mmDCORE0_TPC0_CFG_QM_TID_SIZE_DIM_1 … #define mmDCORE0_TPC0_CFG_QM_TID_BASE_DIM_2 … #define mmDCORE0_TPC0_CFG_QM_TID_SIZE_DIM_2 … #define mmDCORE0_TPC0_CFG_QM_TID_BASE_DIM_3 … #define mmDCORE0_TPC0_CFG_QM_TID_SIZE_DIM_3 … #define mmDCORE0_TPC0_CFG_QM_TID_BASE_DIM_4 … #define mmDCORE0_TPC0_CFG_QM_TID_SIZE_DIM_4 … #define mmDCORE0_TPC0_CFG_QM_KERNEL_CONFIG … #define mmDCORE0_TPC0_CFG_QM_KERNEL_ID … #define mmDCORE0_TPC0_CFG_QM_POWER_LOOP … #define mmDCORE0_TPC0_CFG_QM_SRF_0 … #define mmDCORE0_TPC0_CFG_QM_SRF_1 … #define mmDCORE0_TPC0_CFG_QM_SRF_2 … #define mmDCORE0_TPC0_CFG_QM_SRF_3 … #define mmDCORE0_TPC0_CFG_QM_SRF_4 … #define mmDCORE0_TPC0_CFG_QM_SRF_5 … #define mmDCORE0_TPC0_CFG_QM_SRF_6 … #define mmDCORE0_TPC0_CFG_QM_SRF_7 … #define mmDCORE0_TPC0_CFG_QM_SRF_8 … #define mmDCORE0_TPC0_CFG_QM_SRF_9 … #define mmDCORE0_TPC0_CFG_QM_SRF_10 … #define mmDCORE0_TPC0_CFG_QM_SRF_11 … #define mmDCORE0_TPC0_CFG_QM_SRF_12 … #define mmDCORE0_TPC0_CFG_QM_SRF_13 … #define mmDCORE0_TPC0_CFG_QM_SRF_14 … #define mmDCORE0_TPC0_CFG_QM_SRF_15 … #define mmDCORE0_TPC0_CFG_QM_SRF_16 … #define mmDCORE0_TPC0_CFG_QM_SRF_17 … #define mmDCORE0_TPC0_CFG_QM_SRF_18 … #define mmDCORE0_TPC0_CFG_QM_SRF_19 … #define mmDCORE0_TPC0_CFG_QM_SRF_20 … #define mmDCORE0_TPC0_CFG_QM_SRF_21 … #define mmDCORE0_TPC0_CFG_QM_SRF_22 … #define mmDCORE0_TPC0_CFG_QM_SRF_23 … #define mmDCORE0_TPC0_CFG_QM_SRF_24 … #define mmDCORE0_TPC0_CFG_QM_SRF_25 … #define mmDCORE0_TPC0_CFG_QM_SRF_26 … #define mmDCORE0_TPC0_CFG_QM_SRF_27 … #define mmDCORE0_TPC0_CFG_QM_SRF_28 … #define mmDCORE0_TPC0_CFG_QM_SRF_29 … #define mmDCORE0_TPC0_CFG_QM_SRF_30 … #define mmDCORE0_TPC0_CFG_QM_SRF_31 … #define mmDCORE0_TPC0_CFG_QM_KERNEL_ID_INC … #define mmDCORE0_TPC0_CFG_QM_TID_BASE_SIZE_HIGH_DIM_0 … #define mmDCORE0_TPC0_CFG_QM_TID_BASE_SIZE_HIGH_DIM_1 … #define mmDCORE0_TPC0_CFG_QM_TID_BASE_SIZE_HIGH_DIM_2 … #define mmDCORE0_TPC0_CFG_QM_TID_BASE_SIZE_HIGH_DIM_3 … #define mmDCORE0_TPC0_CFG_QM_TID_BASE_SIZE_HIGH_DIM_4 … #endif /* ASIC_REG_DCORE0_TPC0_CFG_QM_REGS_H_ */
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