/* SPDX-License-Identifier: GPL-2.0 * * Copyright 2016-2020 HabanaLabs, Ltd. * All Rights Reserved. * */ /************************************ ** This is an auto-generated file ** ** DO NOT EDIT BELOW ** ************************************/ #ifndef ASIC_REG_DCORE0_TPC0_CFG_SPECIAL_REGS_H_ #define ASIC_REG_DCORE0_TPC0_CFG_SPECIAL_REGS_H_ /* ***************************************** * DCORE0_TPC0_CFG_SPECIAL * (Prototype: SPECIAL_REGS) ***************************************** */ #define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_PRIV_0 … #define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_PRIV_1 … #define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_PRIV_2 … #define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_PRIV_3 … #define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_PRIV_4 … #define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_PRIV_5 … #define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_PRIV_6 … #define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_PRIV_7 … #define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_PRIV_8 … #define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_PRIV_9 … #define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_PRIV_10 … #define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_PRIV_11 … #define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_PRIV_12 … #define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_PRIV_13 … #define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_PRIV_14 … #define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_PRIV_15 … #define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_PRIV_16 … #define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_PRIV_17 … #define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_PRIV_18 … #define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_PRIV_19 … #define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_PRIV_20 … #define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_PRIV_21 … #define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_PRIV_22 … #define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_PRIV_23 … #define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_PRIV_24 … #define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_PRIV_25 … #define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_PRIV_26 … #define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_PRIV_27 … #define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_PRIV_28 … #define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_PRIV_29 … #define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_PRIV_30 … #define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_PRIV_31 … #define mmDCORE0_TPC0_CFG_SPECIAL_MEM_GW_DATA … #define mmDCORE0_TPC0_CFG_SPECIAL_MEM_GW_REQ … #define mmDCORE0_TPC0_CFG_SPECIAL_MEM_NUMOF … #define mmDCORE0_TPC0_CFG_SPECIAL_MEM_ECC_SEL … #define mmDCORE0_TPC0_CFG_SPECIAL_MEM_ECC_CTL … #define mmDCORE0_TPC0_CFG_SPECIAL_MEM_ECC_ERR_MASK … #define mmDCORE0_TPC0_CFG_SPECIAL_MEM_ECC_GLBL_ERR_MASK … #define mmDCORE0_TPC0_CFG_SPECIAL_MEM_ECC_ERR_STS … #define mmDCORE0_TPC0_CFG_SPECIAL_MEM_ECC_ERR_ADDR … #define mmDCORE0_TPC0_CFG_SPECIAL_MEM_RM … #define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_ERR_MASK … #define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_ERR_ADDR … #define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_ERR_CAUSE … #define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SPARE_0 … #define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SPARE_1 … #define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SPARE_2 … #define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SPARE_3 … #define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SEC_0 … #define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SEC_1 … #define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SEC_2 … #define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SEC_3 … #define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SEC_4 … #define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SEC_5 … #define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SEC_6 … #define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SEC_7 … #define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SEC_8 … #define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SEC_9 … #define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SEC_10 … #define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SEC_11 … #define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SEC_12 … #define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SEC_13 … #define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SEC_14 … #define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SEC_15 … #define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SEC_16 … #define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SEC_17 … #define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SEC_18 … #define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SEC_19 … #define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SEC_20 … #define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SEC_21 … #define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SEC_22 … #define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SEC_23 … #define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SEC_24 … #define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SEC_25 … #define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SEC_26 … #define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SEC_27 … #define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SEC_28 … #define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SEC_29 … #define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SEC_30 … #define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SEC_31 … #endif /* ASIC_REG_DCORE0_TPC0_CFG_SPECIAL_REGS_H_ */
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