/* SPDX-License-Identifier: GPL-2.0 * * Copyright 2016-2020 HabanaLabs, Ltd. * All Rights Reserved. * */ /************************************ ** This is an auto-generated file ** ** DO NOT EDIT BELOW ** ************************************/ #ifndef ASIC_REG_DCORE0_TPC0_EML_STM_REGS_H_ #define ASIC_REG_DCORE0_TPC0_EML_STM_REGS_H_ /* ***************************************** * DCORE0_TPC0_EML_STM * (Prototype: STM) ***************************************** */ #define mmDCORE0_TPC0_EML_STM_STMDMASTARTR … #define mmDCORE0_TPC0_EML_STM_STMDMASTOPR … #define mmDCORE0_TPC0_EML_STM_STMDMASTATR … #define mmDCORE0_TPC0_EML_STM_STMDMACTLR … #define mmDCORE0_TPC0_EML_STM_STMDMAIDR … #define mmDCORE0_TPC0_EML_STM_STMHEER … #define mmDCORE0_TPC0_EML_STM_STMHETER … #define mmDCORE0_TPC0_EML_STM_STMHEBSR … #define mmDCORE0_TPC0_EML_STM_STMHEMCR … #define mmDCORE0_TPC0_EML_STM_STMHEEXTMUXR … #define mmDCORE0_TPC0_EML_STM_STMHEMASTR … #define mmDCORE0_TPC0_EML_STM_STMHEFEAT1R … #define mmDCORE0_TPC0_EML_STM_STMHEIDR … #define mmDCORE0_TPC0_EML_STM_STMSPER … #define mmDCORE0_TPC0_EML_STM_STMSPTER … #define mmDCORE0_TPC0_EML_STM_STMSPSCR … #define mmDCORE0_TPC0_EML_STM_STMSPMSCR … #define mmDCORE0_TPC0_EML_STM_STMSPOVERRIDER … #define mmDCORE0_TPC0_EML_STM_STMSPMOVERRIDER … #define mmDCORE0_TPC0_EML_STM_STMSPTRIGCSR … #define mmDCORE0_TPC0_EML_STM_STMTCSR … #define mmDCORE0_TPC0_EML_STM_STMTSSTIMR … #define mmDCORE0_TPC0_EML_STM_STMTSFREQR … #define mmDCORE0_TPC0_EML_STM_STMSYNCR … #define mmDCORE0_TPC0_EML_STM_STMAUXCR … #define mmDCORE0_TPC0_EML_STM_STMFEAT1R … #define mmDCORE0_TPC0_EML_STM_STMFEAT2R … #define mmDCORE0_TPC0_EML_STM_STMFEAT3R … #define mmDCORE0_TPC0_EML_STM_STMITTRIGGER … #define mmDCORE0_TPC0_EML_STM_STMITATBDATA0 … #define mmDCORE0_TPC0_EML_STM_STMITATBCTR2 … #define mmDCORE0_TPC0_EML_STM_STMITATBID … #define mmDCORE0_TPC0_EML_STM_STMITATBCTR0 … #define mmDCORE0_TPC0_EML_STM_STMITCTRL … #define mmDCORE0_TPC0_EML_STM_STMCLAIMSET … #define mmDCORE0_TPC0_EML_STM_STMCLAIMCLR … #define mmDCORE0_TPC0_EML_STM_STMLAR … #define mmDCORE0_TPC0_EML_STM_STMLSR … #define mmDCORE0_TPC0_EML_STM_STMAUTHSTATUS … #define mmDCORE0_TPC0_EML_STM_STMDEVARCH … #define mmDCORE0_TPC0_EML_STM_STMDEVID … #define mmDCORE0_TPC0_EML_STM_STMDEVTYPE … #define mmDCORE0_TPC0_EML_STM_STMPIDR4 … #define mmDCORE0_TPC0_EML_STM_STMPIDR5 … #define mmDCORE0_TPC0_EML_STM_STMPIDR6 … #define mmDCORE0_TPC0_EML_STM_STMPIDR7 … #define mmDCORE0_TPC0_EML_STM_STMPIDR0 … #define mmDCORE0_TPC0_EML_STM_STMPIDR1 … #define mmDCORE0_TPC0_EML_STM_STMPIDR2 … #define mmDCORE0_TPC0_EML_STM_STMPIDR3 … #define mmDCORE0_TPC0_EML_STM_STMCIDR0 … #define mmDCORE0_TPC0_EML_STM_STMCIDR1 … #define mmDCORE0_TPC0_EML_STM_STMCIDR2 … #define mmDCORE0_TPC0_EML_STM_STMCIDR3 … #endif /* ASIC_REG_DCORE0_TPC0_EML_STM_REGS_H_ */
Codebase Browser
linux