/* SPDX-License-Identifier: GPL-2.0 * * Copyright 2016-2020 HabanaLabs, Ltd. * All Rights Reserved. * */ /************************************ ** This is an auto-generated file ** ** DO NOT EDIT BELOW ** ************************************/ #ifndef ASIC_REG_DCORE0_TPC0_EML_SPMU_REGS_H_ #define ASIC_REG_DCORE0_TPC0_EML_SPMU_REGS_H_ /* ***************************************** * DCORE0_TPC0_EML_SPMU * (Prototype: SPMU) ***************************************** */ #define mmDCORE0_TPC0_EML_SPMU_PMEVCNTR0_EL0 … #define mmDCORE0_TPC0_EML_SPMU_PMEVCNTR1_EL0 … #define mmDCORE0_TPC0_EML_SPMU_PMEVCNTR2_EL0 … #define mmDCORE0_TPC0_EML_SPMU_PMEVCNTR3_EL0 … #define mmDCORE0_TPC0_EML_SPMU_PMEVCNTR4_EL0 … #define mmDCORE0_TPC0_EML_SPMU_PMEVCNTR5_EL0 … #define mmDCORE0_TPC0_EML_SPMU_PMCCNTR_L_EL0 … #define mmDCORE0_TPC0_EML_SPMU_PMCCNTR_H_EL0 … #define mmDCORE0_TPC0_EML_SPMU_PMTRC … #define mmDCORE0_TPC0_EML_SPMU_TRC_CTRL_HOST … #define mmDCORE0_TPC0_EML_SPMU_TRC_STAT_HOST … #define mmDCORE0_TPC0_EML_SPMU_TRC_EN_HOST … #define mmDCORE0_TPC0_EML_SPMU_PMEVTYPER0_EL0 … #define mmDCORE0_TPC0_EML_SPMU_PMEVTYPER1_EL0 … #define mmDCORE0_TPC0_EML_SPMU_PMEVTYPER2_EL0 … #define mmDCORE0_TPC0_EML_SPMU_PMEVTYPER3_EL0 … #define mmDCORE0_TPC0_EML_SPMU_PMEVTYPER4_EL0 … #define mmDCORE0_TPC0_EML_SPMU_PMEVTYPER5_EL0 … #define mmDCORE0_TPC0_EML_SPMU_PMSSR … #define mmDCORE0_TPC0_EML_SPMU_PMOVSSR … #define mmDCORE0_TPC0_EML_SPMU_PMCCNTSR_L … #define mmDCORE0_TPC0_EML_SPMU_PMCCNTSR_H … #define mmDCORE0_TPC0_EML_SPMU_PMEVCNTSR0 … #define mmDCORE0_TPC0_EML_SPMU_PMEVCNTSR1 … #define mmDCORE0_TPC0_EML_SPMU_PMEVCNTSR2 … #define mmDCORE0_TPC0_EML_SPMU_PMEVCNTSR3 … #define mmDCORE0_TPC0_EML_SPMU_PMEVCNTSR4 … #define mmDCORE0_TPC0_EML_SPMU_PMEVCNTSR5 … #define mmDCORE0_TPC0_EML_SPMU_PMSCR … #define mmDCORE0_TPC0_EML_SPMU_PMSRR … #define mmDCORE0_TPC0_EML_SPMU_PMCNTENSET_EL0 … #define mmDCORE0_TPC0_EML_SPMU_PMCNTENCLR_EL0 … #define mmDCORE0_TPC0_EML_SPMU_PMINTENSET_EL1 … #define mmDCORE0_TPC0_EML_SPMU_PMINTENCLR_EL1 … #define mmDCORE0_TPC0_EML_SPMU_PMOVSCLR_EL0 … #define mmDCORE0_TPC0_EML_SPMU_PMSWINC_EL0 … #define mmDCORE0_TPC0_EML_SPMU_PMOVSSET_EL0 … #define mmDCORE0_TPC0_EML_SPMU_PMCFGR … #define mmDCORE0_TPC0_EML_SPMU_PMCR_EL0 … #define mmDCORE0_TPC0_EML_SPMU_PMITCTRL … #define mmDCORE0_TPC0_EML_SPMU_PMCLAIMSET … #define mmDCORE0_TPC0_EML_SPMU_PMCLAIMCLR … #define mmDCORE0_TPC0_EML_SPMU_PMDEVAFF0 … #define mmDCORE0_TPC0_EML_SPMU_PMDEVAFF1 … #define mmDCORE0_TPC0_EML_SPMU_PMLAR … #define mmDCORE0_TPC0_EML_SPMU_PMLSR … #define mmDCORE0_TPC0_EML_SPMU_PMAUTHSTATUS … #define mmDCORE0_TPC0_EML_SPMU_PMDEVARCH … #define mmDCORE0_TPC0_EML_SPMU_PMDEVID2 … #define mmDCORE0_TPC0_EML_SPMU_PMDEVID1 … #define mmDCORE0_TPC0_EML_SPMU_PMDEVID … #define mmDCORE0_TPC0_EML_SPMU_PMDEVTYPE … #define mmDCORE0_TPC0_EML_SPMU_PMPIDR4 … #define mmDCORE0_TPC0_EML_SPMU_PMPIDR5 … #define mmDCORE0_TPC0_EML_SPMU_PMPIDR6 … #define mmDCORE0_TPC0_EML_SPMU_PMPIDR7 … #define mmDCORE0_TPC0_EML_SPMU_PMPIDR0 … #define mmDCORE0_TPC0_EML_SPMU_PMPIDR1 … #define mmDCORE0_TPC0_EML_SPMU_PMPIDR2 … #define mmDCORE0_TPC0_EML_SPMU_PMPIDR3 … #define mmDCORE0_TPC0_EML_SPMU_PMCIDR0 … #define mmDCORE0_TPC0_EML_SPMU_PMCIDR1 … #define mmDCORE0_TPC0_EML_SPMU_PMCIDR2 … #define mmDCORE0_TPC0_EML_SPMU_PMCIDR3 … #endif /* ASIC_REG_DCORE0_TPC0_EML_SPMU_REGS_H_ */
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