/* SPDX-License-Identifier: GPL-2.0 * * Copyright 2016-2020 HabanaLabs, Ltd. * All Rights Reserved. * */ /************************************ ** This is an auto-generated file ** ** DO NOT EDIT BELOW ** ************************************/ #ifndef ASIC_REG_DCORE0_EDMA0_CORE_REGS_H_ #define ASIC_REG_DCORE0_EDMA0_CORE_REGS_H_ /* ***************************************** * DCORE0_EDMA0_CORE * (Prototype: DMA_CORE) ***************************************** */ #define mmDCORE0_EDMA0_CORE_CFG_0 … #define mmDCORE0_EDMA0_CORE_CFG_1 … #define mmDCORE0_EDMA0_CORE_PROT … #define mmDCORE0_EDMA0_CORE_CKG … #define mmDCORE0_EDMA0_CORE_RD_GLBL … #define mmDCORE0_EDMA0_CORE_RD_HBW_MAX_OUTSTAND … #define mmDCORE0_EDMA0_CORE_RD_HBW_MAX_SIZE … #define mmDCORE0_EDMA0_CORE_RD_HBW_ARCACHE … #define mmDCORE0_EDMA0_CORE_RD_HBW_INFLIGHTS … #define mmDCORE0_EDMA0_CORE_RD_HBW_RATE_LIM_CFG … #define mmDCORE0_EDMA0_CORE_RD_LBW_MAX_OUTSTAND … #define mmDCORE0_EDMA0_CORE_RD_LBW_MAX_SIZE … #define mmDCORE0_EDMA0_CORE_RD_LBW_ARCACHE … #define mmDCORE0_EDMA0_CORE_RD_LBW_INFLIGHTS … #define mmDCORE0_EDMA0_CORE_RD_LBW_RATE_LIM_CFG … #define mmDCORE0_EDMA0_CORE_WR_HBW_MAX_OUTSTAND … #define mmDCORE0_EDMA0_CORE_WR_HBW_MAX_AWID … #define mmDCORE0_EDMA0_CORE_WR_HBW_AWCACHE … #define mmDCORE0_EDMA0_CORE_WR_HBW_INFLIGHTS … #define mmDCORE0_EDMA0_CORE_WR_HBW_RATE_LIM_CFG … #define mmDCORE0_EDMA0_CORE_WR_LBW_MAX_OUTSTAND … #define mmDCORE0_EDMA0_CORE_WR_LBW_MAX_AWID … #define mmDCORE0_EDMA0_CORE_WR_LBW_AWCACHE … #define mmDCORE0_EDMA0_CORE_WR_LBW_INFLIGHTS … #define mmDCORE0_EDMA0_CORE_WR_LBW_RATE_LIM_CFG … #define mmDCORE0_EDMA0_CORE_WR_COMP_MAX_OUTSTAND … #define mmDCORE0_EDMA0_CORE_WR_COMP_AWUSER … #define mmDCORE0_EDMA0_CORE_ERR_CFG … #define mmDCORE0_EDMA0_CORE_ERR_CAUSE … #define mmDCORE0_EDMA0_CORE_ERRMSG_ADDR_LO … #define mmDCORE0_EDMA0_CORE_ERRMSG_ADDR_HI … #define mmDCORE0_EDMA0_CORE_ERRMSG_WDATA … #define mmDCORE0_EDMA0_CORE_STS0 … #define mmDCORE0_EDMA0_CORE_STS1 … #define mmDCORE0_EDMA0_CORE_STS_RD_CTX_SEL … #define mmDCORE0_EDMA0_CORE_STS_RD_CTX_SIZE … #define mmDCORE0_EDMA0_CORE_STS_RD_CTX_BASE_LO … #define mmDCORE0_EDMA0_CORE_STS_RD_CTX_BASE_HI … #define mmDCORE0_EDMA0_CORE_STS_RD_CTX_ID … #define mmDCORE0_EDMA0_CORE_STS_RD_HB_AXI_ADDR_LO … #define mmDCORE0_EDMA0_CORE_STS_RD_HB_AXI_ADDR_HI … #define mmDCORE0_EDMA0_CORE_STS_RD_LB_AXI_ADDR … #define mmDCORE0_EDMA0_CORE_STS_WR_CTX_SEL … #define mmDCORE0_EDMA0_CORE_STS_WR_CTX_SIZE … #define mmDCORE0_EDMA0_CORE_STS_WR_CTX_BASE_LO … #define mmDCORE0_EDMA0_CORE_STS_WR_CTX_BASE_HI … #define mmDCORE0_EDMA0_CORE_STS_WR_CTX_ID … #define mmDCORE0_EDMA0_CORE_STS_WR_HB_AXI_ADDR_LO … #define mmDCORE0_EDMA0_CORE_STS_WR_HB_AXI_ADDR_HI … #define mmDCORE0_EDMA0_CORE_STS_WR_LB_AXI_ADDR … #define mmDCORE0_EDMA0_CORE_PWRLP_CFG … #define mmDCORE0_EDMA0_CORE_PWRLP_STS … #define mmDCORE0_EDMA0_CORE_DBG_DESC_CNT … #define mmDCORE0_EDMA0_CORE_DBG_STS … #define mmDCORE0_EDMA0_CORE_DBG_BUF_STS … #define mmDCORE0_EDMA0_CORE_DBG_RD_DESC_ID … #define mmDCORE0_EDMA0_CORE_DBG_WR_DESC_ID … #define mmDCORE0_EDMA0_CORE_APB_DMA_LBW_BASE … #define mmDCORE0_EDMA0_CORE_APB_MSTR_IF_LBW_BASE … #define mmDCORE0_EDMA0_CORE_E2E_CRED_ASYNC_CFG … #define mmDCORE0_EDMA0_CORE_DBG_APB_ENABLER … #define mmDCORE0_EDMA0_CORE_L2H_CMPR_LO … #define mmDCORE0_EDMA0_CORE_L2H_CMPR_HI … #define mmDCORE0_EDMA0_CORE_L2H_MASK_LO … #define mmDCORE0_EDMA0_CORE_L2H_MASK_HI … #define mmDCORE0_EDMA0_CORE_IDLE_IND_MASK … #define mmDCORE0_EDMA0_CORE_APB_ENABLER … #endif /* ASIC_REG_DCORE0_EDMA0_CORE_REGS_H_ */
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