/* SPDX-License-Identifier: GPL-2.0 * * Copyright 2016-2020 HabanaLabs, Ltd. * All Rights Reserved. * */ /************************************ ** This is an auto-generated file ** ** DO NOT EDIT BELOW ** ************************************/ #ifndef ASIC_REG_DCORE0_EDMA0_CORE_CTX_REGS_H_ #define ASIC_REG_DCORE0_EDMA0_CORE_CTX_REGS_H_ /* ***************************************** * DCORE0_EDMA0_CORE_CTX * (Prototype: DMA_CORE_CTX) ***************************************** */ #define mmDCORE0_EDMA0_CORE_CTX_RATE_LIM_TKN … #define mmDCORE0_EDMA0_CORE_CTX_PWRLP … #define mmDCORE0_EDMA0_CORE_CTX_TE_NUMROWS … #define mmDCORE0_EDMA0_CORE_CTX_IDX … #define mmDCORE0_EDMA0_CORE_CTX_IDX_INC … #define mmDCORE0_EDMA0_CORE_CTX_CTRL … #define mmDCORE0_EDMA0_CORE_CTX_SRC_TSIZE_0 … #define mmDCORE0_EDMA0_CORE_CTX_SRC_TSIZE_1 … #define mmDCORE0_EDMA0_CORE_CTX_SRC_STRIDE_1 … #define mmDCORE0_EDMA0_CORE_CTX_SRC_TSIZE_2 … #define mmDCORE0_EDMA0_CORE_CTX_SRC_STRIDE_2 … #define mmDCORE0_EDMA0_CORE_CTX_SRC_TSIZE_3 … #define mmDCORE0_EDMA0_CORE_CTX_SRC_STRIDE_3 … #define mmDCORE0_EDMA0_CORE_CTX_SRC_TSIZE_4 … #define mmDCORE0_EDMA0_CORE_CTX_SRC_STRIDE_4 … #define mmDCORE0_EDMA0_CORE_CTX_DST_TSIZE_1 … #define mmDCORE0_EDMA0_CORE_CTX_DST_STRIDE_1 … #define mmDCORE0_EDMA0_CORE_CTX_DST_TSIZE_2 … #define mmDCORE0_EDMA0_CORE_CTX_DST_STRIDE_2 … #define mmDCORE0_EDMA0_CORE_CTX_DST_TSIZE_3 … #define mmDCORE0_EDMA0_CORE_CTX_DST_STRIDE_3 … #define mmDCORE0_EDMA0_CORE_CTX_DST_TSIZE_4 … #define mmDCORE0_EDMA0_CORE_CTX_DST_STRIDE_4 … #define mmDCORE0_EDMA0_CORE_CTX_WR_COMP_ADDR_HI … #define mmDCORE0_EDMA0_CORE_CTX_WR_COMP_ADDR_LO … #define mmDCORE0_EDMA0_CORE_CTX_WR_COMP_WDATA … #define mmDCORE0_EDMA0_CORE_CTX_SRC_OFFSET_LO … #define mmDCORE0_EDMA0_CORE_CTX_SRC_OFFSET_HI … #define mmDCORE0_EDMA0_CORE_CTX_DST_OFFSET_LO … #define mmDCORE0_EDMA0_CORE_CTX_DST_OFFSET_HI … #define mmDCORE0_EDMA0_CORE_CTX_SRC_BASE_LO … #define mmDCORE0_EDMA0_CORE_CTX_SRC_BASE_HI … #define mmDCORE0_EDMA0_CORE_CTX_DST_BASE_LO … #define mmDCORE0_EDMA0_CORE_CTX_DST_BASE_HI … #define mmDCORE0_EDMA0_CORE_CTX_DST_TSIZE_0 … #define mmDCORE0_EDMA0_CORE_CTX_COMMIT … #endif /* ASIC_REG_DCORE0_EDMA0_CORE_CTX_REGS_H_ */
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