/* SPDX-License-Identifier: GPL-2.0 * * Copyright 2016-2020 HabanaLabs, Ltd. * All Rights Reserved. * */ /************************************ ** This is an auto-generated file ** ** DO NOT EDIT BELOW ** ************************************/ #ifndef ASIC_REG_DCORE0_HMMU0_STLB_REGS_H_ #define ASIC_REG_DCORE0_HMMU0_STLB_REGS_H_ /* ***************************************** * DCORE0_HMMU0_STLB * (Prototype: STLB) ***************************************** */ #define mmDCORE0_HMMU0_STLB_BUSY … #define mmDCORE0_HMMU0_STLB_ASID … #define mmDCORE0_HMMU0_STLB_HOP0_PA43_12 … #define mmDCORE0_HMMU0_STLB_HOP0_PA63_44 … #define mmDCORE0_HMMU0_STLB_CACHE_INV … #define mmDCORE0_HMMU0_STLB_CACHE_INV_BASE_39_8 … #define mmDCORE0_HMMU0_STLB_CACHE_INV_BASE_63_40 … #define mmDCORE0_HMMU0_STLB_STLB_FEATURE_EN … #define mmDCORE0_HMMU0_STLB_STLB_AXI_CACHE … #define mmDCORE0_HMMU0_STLB_HOP_CONFIGURATION … #define mmDCORE0_HMMU0_STLB_LINK_LIST_LOOKUP_MASK_63_32 … #define mmDCORE0_HMMU0_STLB_LINK_LIST_LOOKUP_MASK_31_0 … #define mmDCORE0_HMMU0_STLB_INV_ALL_START … #define mmDCORE0_HMMU0_STLB_INV_ALL_SET … #define mmDCORE0_HMMU0_STLB_INV_PS … #define mmDCORE0_HMMU0_STLB_INV_CONSUMER_INDEX … #define mmDCORE0_HMMU0_STLB_INV_HIT_COUNT … #define mmDCORE0_HMMU0_STLB_INV_SET … #define mmDCORE0_HMMU0_STLB_SRAM_INIT … #define mmDCORE0_HMMU0_STLB_MEM_CACHE_INVALIDATION … #define mmDCORE0_HMMU0_STLB_MEM_CACHE_INV_STATUS … #define mmDCORE0_HMMU0_STLB_MEM_CACHE_BASE_38_7 … #define mmDCORE0_HMMU0_STLB_MEM_CACHE_BASE_63_39 … #define mmDCORE0_HMMU0_STLB_MEM_CACHE_CONFIG … #define mmDCORE0_HMMU0_STLB_SET_THRESHOLD_HOP5 … #define mmDCORE0_HMMU0_STLB_SET_THRESHOLD_HOP4 … #define mmDCORE0_HMMU0_STLB_SET_THRESHOLD_HOP3 … #define mmDCORE0_HMMU0_STLB_SET_THRESHOLD_HOP2 … #define mmDCORE0_HMMU0_STLB_SET_THRESHOLD_HOP1 … #define mmDCORE0_HMMU0_STLB_SET_THRESHOLD_HOP0 … #define mmDCORE0_HMMU0_STLB_MULTI_HIT_INTERRUPT_CLR … #define mmDCORE0_HMMU0_STLB_MULTI_HIT_INTERRUPT_MASK … #define mmDCORE0_HMMU0_STLB_MEM_L0_CACHE_CFG … #define mmDCORE0_HMMU0_STLB_MEM_READ_ARPROT … #define mmDCORE0_HMMU0_STLB_RANGE_CACHE_INVALIDATION … #define mmDCORE0_HMMU0_STLB_RANGE_INV_START_LSB … #define mmDCORE0_HMMU0_STLB_RANGE_INV_START_MSB … #define mmDCORE0_HMMU0_STLB_RANGE_INV_END_LSB … #define mmDCORE0_HMMU0_STLB_RANGE_INV_END_MSB … #define mmDCORE0_HMMU0_STLB_ASID_SCRAMBLER_CTRL … #define mmDCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_0 … #define mmDCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_1 … #define mmDCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_2 … #define mmDCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_3 … #define mmDCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_4 … #define mmDCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_5 … #define mmDCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_6 … #define mmDCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_7 … #define mmDCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_8 … #define mmDCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_9 … #define mmDCORE0_HMMU0_STLB_ASID_SCR_POLY_MAT_H3_10 … #define mmDCORE0_HMMU0_STLB_ASID_SCR_POLY_MAT_H3_11 … #define mmDCORE0_HMMU0_STLB_ASID_SCR_POLY_MAT_H3_12 … #define mmDCORE0_HMMU0_STLB_ASID_SCR_POLY_MAT_H3_13 … #define mmDCORE0_HMMU0_STLB_ASID_SCR_POLY_MAT_H3_14 … #define mmDCORE0_HMMU0_STLB_ASID_SCR_POLY_MAT_H3_15 … #define mmDCORE0_HMMU0_STLB_ASID_SCR_POLY_MAT_H3_16 … #define mmDCORE0_HMMU0_STLB_ASID_SCR_POLY_MAT_H3_17 … #define mmDCORE0_HMMU0_STLB_ASID_SCR_POLY_MAT_H3_18 … #endif /* ASIC_REG_DCORE0_HMMU0_STLB_REGS_H_ */
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