/* SPDX-License-Identifier: GPL-2.0 * * Copyright 2016-2020 HabanaLabs, Ltd. * All Rights Reserved. * */ /************************************ ** This is an auto-generated file ** ** DO NOT EDIT BELOW ** ************************************/ #ifndef ASIC_REG_DCORE0_HMMU0_MMU_REGS_H_ #define ASIC_REG_DCORE0_HMMU0_MMU_REGS_H_ /* ***************************************** * DCORE0_HMMU0_MMU * (Prototype: MMU) ***************************************** */ #define mmDCORE0_HMMU0_MMU_MMU_ENABLE … #define mmDCORE0_HMMU0_MMU_FORCE_ORDERING … #define mmDCORE0_HMMU0_MMU_FEATURE_ENABLE … #define mmDCORE0_HMMU0_MMU_VA_ORDERING_MASK_38_7 … #define mmDCORE0_HMMU0_MMU_VA_ORDERING_MASK_64_39 … #define mmDCORE0_HMMU0_MMU_LOG2_DDR_SIZE … #define mmDCORE0_HMMU0_MMU_SCRAMBLER … #define mmDCORE0_HMMU0_MMU_MEM_INIT_BUSY … #define mmDCORE0_HMMU0_MMU_SPI_SEI_MASK … #define mmDCORE0_HMMU0_MMU_SPI_SEI_CAUSE … #define mmDCORE0_HMMU0_MMU_PAGE_ERROR_CAPTURE … #define mmDCORE0_HMMU0_MMU_PAGE_ERROR_CAPTURE_VA … #define mmDCORE0_HMMU0_MMU_ACCESS_ERROR_CAPTURE … #define mmDCORE0_HMMU0_MMU_ACCESS_ERROR_CAPTURE_VA … #define mmDCORE0_HMMU0_MMU_ACCESS_PAGE_ERROR_VALID … #define mmDCORE0_HMMU0_MMU_INTERRUPT_CLR … #define mmDCORE0_HMMU0_MMU_INTERRUPT_MASK … #define mmDCORE0_HMMU0_MMU_DBG_MEM_WRAP_RM … #define mmDCORE0_HMMU0_MMU_SPI_CAUSE_CLR … #define mmDCORE0_HMMU0_MMU_PIPE_CREDIT … #define mmDCORE0_HMMU0_MMU_MMU_BYPASS … #define mmDCORE0_HMMU0_MMU_STATIC_MULTI_PAGE_SIZE … #define mmDCORE0_HMMU0_MMU_CORE_SEP_CACHE_RNG … #define mmDCORE0_HMMU0_MMU_CORE_SEP_SLICE_CRDT … #define mmDCORE0_HMMU0_MMU_TOTAL_SLICE_CREDIT … #define mmDCORE0_HMMU0_MMU_PAGE_FAULT_ID_LSB … #define mmDCORE0_HMMU0_MMU_PAGE_FAULT_ID_MSB … #define mmDCORE0_HMMU0_MMU_PAGE_ACCESS_ID_LSB … #define mmDCORE0_HMMU0_MMU_PAGE_ACCESS_ID_MSB … #define mmDCORE0_HMMU0_MMU_DDR_RANGE_REG_ENABLE … #define mmDCORE0_HMMU0_MMU_MMU_RR_SEC_MIN_63_32_0 … #define mmDCORE0_HMMU0_MMU_MMU_RR_SEC_MIN_63_32_1 … #define mmDCORE0_HMMU0_MMU_MMU_RR_SEC_MIN_63_32_2 … #define mmDCORE0_HMMU0_MMU_MMU_RR_SEC_MIN_63_32_3 … #define mmDCORE0_HMMU0_MMU_MMU_RR_SEC_MIN_63_32_4 … #define mmDCORE0_HMMU0_MMU_MMU_RR_SEC_MIN_63_32_5 … #define mmDCORE0_HMMU0_MMU_MMU_RR_SEC_MIN_63_32_6 … #define mmDCORE0_HMMU0_MMU_MMU_RR_SEC_MIN_63_32_7 … #define mmDCORE0_HMMU0_MMU_MMU_RR_SEC_MIN_31_0_0 … #define mmDCORE0_HMMU0_MMU_MMU_RR_SEC_MIN_31_0_1 … #define mmDCORE0_HMMU0_MMU_MMU_RR_SEC_MIN_31_0_2 … #define mmDCORE0_HMMU0_MMU_MMU_RR_SEC_MIN_31_0_3 … #define mmDCORE0_HMMU0_MMU_MMU_RR_SEC_MIN_31_0_4 … #define mmDCORE0_HMMU0_MMU_MMU_RR_SEC_MIN_31_0_5 … #define mmDCORE0_HMMU0_MMU_MMU_RR_SEC_MIN_31_0_6 … #define mmDCORE0_HMMU0_MMU_MMU_RR_SEC_MIN_31_0_7 … #define mmDCORE0_HMMU0_MMU_MMU_RR_SEC_MAX_63_32_0 … #define mmDCORE0_HMMU0_MMU_MMU_RR_SEC_MAX_63_32_1 … #define mmDCORE0_HMMU0_MMU_MMU_RR_SEC_MAX_63_32_2 … #define mmDCORE0_HMMU0_MMU_MMU_RR_SEC_MAX_63_32_3 … #define mmDCORE0_HMMU0_MMU_MMU_RR_SEC_MAX_63_32_4 … #define mmDCORE0_HMMU0_MMU_MMU_RR_SEC_MAX_63_32_5 … #define mmDCORE0_HMMU0_MMU_MMU_RR_SEC_MAX_63_32_6 … #define mmDCORE0_HMMU0_MMU_MMU_RR_SEC_MAX_63_32_7 … #define mmDCORE0_HMMU0_MMU_MMU_RR_SEC_MAX_31_0_0 … #define mmDCORE0_HMMU0_MMU_MMU_RR_SEC_MAX_31_0_1 … #define mmDCORE0_HMMU0_MMU_MMU_RR_SEC_MAX_31_0_2 … #define mmDCORE0_HMMU0_MMU_MMU_RR_SEC_MAX_31_0_3 … #define mmDCORE0_HMMU0_MMU_MMU_RR_SEC_MAX_31_0_4 … #define mmDCORE0_HMMU0_MMU_MMU_RR_SEC_MAX_31_0_5 … #define mmDCORE0_HMMU0_MMU_MMU_RR_SEC_MAX_31_0_6 … #define mmDCORE0_HMMU0_MMU_MMU_RR_SEC_MAX_31_0_7 … #define mmDCORE0_HMMU0_MMU_MMU_RR_PRIV_MIN_63_32_0 … #define mmDCORE0_HMMU0_MMU_MMU_RR_PRIV_MIN_63_32_1 … #define mmDCORE0_HMMU0_MMU_MMU_RR_PRIV_MIN_63_32_2 … #define mmDCORE0_HMMU0_MMU_MMU_RR_PRIV_MIN_63_32_3 … #define mmDCORE0_HMMU0_MMU_MMU_RR_PRIV_MIN_63_32_4 … #define mmDCORE0_HMMU0_MMU_MMU_RR_PRIV_MIN_63_32_5 … #define mmDCORE0_HMMU0_MMU_MMU_RR_PRIV_MIN_63_32_6 … #define mmDCORE0_HMMU0_MMU_MMU_RR_PRIV_MIN_63_32_7 … #define mmDCORE0_HMMU0_MMU_MMU_RR_PRIV_MIN_31_0_0 … #define mmDCORE0_HMMU0_MMU_MMU_RR_PRIV_MIN_31_0_1 … #define mmDCORE0_HMMU0_MMU_MMU_RR_PRIV_MIN_31_0_2 … #define mmDCORE0_HMMU0_MMU_MMU_RR_PRIV_MIN_31_0_3 … #define mmDCORE0_HMMU0_MMU_MMU_RR_PRIV_MIN_31_0_4 … #define mmDCORE0_HMMU0_MMU_MMU_RR_PRIV_MIN_31_0_5 … #define mmDCORE0_HMMU0_MMU_MMU_RR_PRIV_MIN_31_0_6 … #define mmDCORE0_HMMU0_MMU_MMU_RR_PRIV_MIN_31_0_7 … #define mmDCORE0_HMMU0_MMU_MMU_RR_PRIV_MAX_63_32_0 … #define mmDCORE0_HMMU0_MMU_MMU_RR_PRIV_MAX_63_32_1 … #define mmDCORE0_HMMU0_MMU_MMU_RR_PRIV_MAX_63_32_2 … #define mmDCORE0_HMMU0_MMU_MMU_RR_PRIV_MAX_63_32_3 … #define mmDCORE0_HMMU0_MMU_MMU_RR_PRIV_MAX_63_32_4 … #define mmDCORE0_HMMU0_MMU_MMU_RR_PRIV_MAX_63_32_5 … #define mmDCORE0_HMMU0_MMU_MMU_RR_PRIV_MAX_63_32_6 … #define mmDCORE0_HMMU0_MMU_MMU_RR_PRIV_MAX_63_32_7 … #define mmDCORE0_HMMU0_MMU_MMU_RR_PRIV_MAX_31_0_0 … #define mmDCORE0_HMMU0_MMU_MMU_RR_PRIV_MAX_31_0_1 … #define mmDCORE0_HMMU0_MMU_MMU_RR_PRIV_MAX_31_0_2 … #define mmDCORE0_HMMU0_MMU_MMU_RR_PRIV_MAX_31_0_3 … #define mmDCORE0_HMMU0_MMU_MMU_RR_PRIV_MAX_31_0_4 … #define mmDCORE0_HMMU0_MMU_MMU_RR_PRIV_MAX_31_0_5 … #define mmDCORE0_HMMU0_MMU_MMU_RR_PRIV_MAX_31_0_6 … #define mmDCORE0_HMMU0_MMU_MMU_RR_PRIV_MAX_31_0_7 … #define mmDCORE0_HMMU0_MMU_ILLEGAL_ADDR_WRITE_63_32 … #define mmDCORE0_HMMU0_MMU_ILLEGAL_ADDR_WRITE_31_0 … #define mmDCORE0_HMMU0_MMU_ILLEGAL_ADDR_READ_63_32 … #define mmDCORE0_HMMU0_MMU_ILLEGAL_ADDR_READ_31_0 … #define mmDCORE0_HMMU0_MMU_RAZWI_WRITE_VLD … #define mmDCORE0_HMMU0_MMU_RAZWI_WRITE_ID_31_0 … #define mmDCORE0_HMMU0_MMU_RAZWI_WRITE_ID_42_32 … #define mmDCORE0_HMMU0_MMU_RAZWI_READ_VLD … #define mmDCORE0_HMMU0_MMU_RAZWI_READ_ID_31_0 … #define mmDCORE0_HMMU0_MMU_RAZWI_READ_ID_42_32 … #define mmDCORE0_HMMU0_MMU_MMU_SRC_NUM … #define mmDCORE0_HMMU0_MMU_RAZWI_ADDR_LSB … #define mmDCORE0_HMMU0_MMU_RAZWI_ADDR_MSB … #endif /* ASIC_REG_DCORE0_HMMU0_MMU_REGS_H_ */
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