/* SPDX-License-Identifier: GPL-2.0 * * Copyright 2016-2020 HabanaLabs, Ltd. * All Rights Reserved. * */ /************************************ ** This is an auto-generated file ** ** DO NOT EDIT BELOW ** ************************************/ #ifndef ASIC_REG_DCORE0_RTR0_CTRL_REGS_H_ #define ASIC_REG_DCORE0_RTR0_CTRL_REGS_H_ /* ***************************************** * DCORE0_RTR0_CTRL * (Prototype: RTR_CTRL) ***************************************** */ #define mmDCORE0_RTR0_CTRL_MEM_NUM … #define mmDCORE0_RTR0_CTRL_MEM_MAP … #define mmDCORE0_RTR0_CTRL_WR_RL_MEM … #define mmDCORE0_RTR0_CTRL_WR_RL_PCI … #define mmDCORE0_RTR0_CTRL_WR_RL_SRAM … #define mmDCORE0_RTR0_CTRL_RD_RL_MEM … #define mmDCORE0_RTR0_CTRL_RD_RL_PCI … #define mmDCORE0_RTR0_CTRL_RD_RL_SRAM … #define mmDCORE0_RTR0_CTRL_WR_RL_MEM_RED … #define mmDCORE0_RTR0_CTRL_RL_MEM_REDUCTION … #define mmDCORE0_RTR0_CTRL_WR_RL_SRAM_RED … #define mmDCORE0_RTR0_CTRL_RGL_SRAM_CFG_0 … #define mmDCORE0_RTR0_CTRL_RGL_SRAM_CFG_1 … #define mmDCORE0_RTR0_CTRL_RGL_SRAM_SHIFT_0 … #define mmDCORE0_RTR0_CTRL_RGL_SRAM_SHIFT_1 … #define mmDCORE0_RTR0_CTRL_RGL_SRAM_EXPECTED_LAT_0 … #define mmDCORE0_RTR0_CTRL_RGL_SRAM_EXPECTED_LAT_1 … #define mmDCORE0_RTR0_CTRL_RGL_SRAM_EXPECTED_LAT_2 … #define mmDCORE0_RTR0_CTRL_RGL_SRAM_EXPECTED_LAT_3 … #define mmDCORE0_RTR0_CTRL_RGL_SRAM_EXPECTED_LAT_4 … #define mmDCORE0_RTR0_CTRL_RGL_SRAM_EXPECTED_LAT_5 … #define mmDCORE0_RTR0_CTRL_RGL_SRAM_EXPECTED_LAT_6 … #define mmDCORE0_RTR0_CTRL_RGL_SRAM_EXPECTED_LAT_7 … #define mmDCORE0_RTR0_CTRL_RGL_SRAM_EXPECTED_LAT_8 … #define mmDCORE0_RTR0_CTRL_RGL_SRAM_EXPECTED_LAT_9 … #define mmDCORE0_RTR0_CTRL_RGL_SRAM_EXPECTED_LAT_10 … #define mmDCORE0_RTR0_CTRL_RGL_SRAM_EXPECTED_LAT_11 … #define mmDCORE0_RTR0_CTRL_RGL_SRAM_EXPECTED_LAT_12 … #define mmDCORE0_RTR0_CTRL_RGL_SRAM_EXPECTED_LAT_13 … #define mmDCORE0_RTR0_CTRL_RGL_SRAM_EXPECTED_LAT_14 … #define mmDCORE0_RTR0_CTRL_RGL_SRAM_EXPECTED_LAT_15 … #define mmDCORE0_RTR0_CTRL_RGL_SRAM_TOKEN_0 … #define mmDCORE0_RTR0_CTRL_RGL_SRAM_TOKEN_1 … #define mmDCORE0_RTR0_CTRL_RGL_SRAM_TOKEN_2 … #define mmDCORE0_RTR0_CTRL_RGL_SRAM_TOKEN_3 … #define mmDCORE0_RTR0_CTRL_RGL_SRAM_TOKEN_4 … #define mmDCORE0_RTR0_CTRL_RGL_SRAM_TOKEN_5 … #define mmDCORE0_RTR0_CTRL_RGL_SRAM_TOKEN_6 … #define mmDCORE0_RTR0_CTRL_RGL_SRAM_TOKEN_7 … #define mmDCORE0_RTR0_CTRL_RGL_SRAM_TOKEN_8 … #define mmDCORE0_RTR0_CTRL_RGL_SRAM_TOKEN_9 … #define mmDCORE0_RTR0_CTRL_RGL_SRAM_TOKEN_10 … #define mmDCORE0_RTR0_CTRL_RGL_SRAM_TOKEN_11 … #define mmDCORE0_RTR0_CTRL_RGL_SRAM_TOKEN_12 … #define mmDCORE0_RTR0_CTRL_RGL_SRAM_TOKEN_13 … #define mmDCORE0_RTR0_CTRL_RGL_SRAM_TOKEN_14 … #define mmDCORE0_RTR0_CTRL_RGL_SRAM_TOKEN_15 … #define mmDCORE0_RTR0_CTRL_RGL_SRAM_BANK_ID_0 … #define mmDCORE0_RTR0_CTRL_RGL_SRAM_BANK_ID_1 … #define mmDCORE0_RTR0_CTRL_RGL_SRAM_BANK_ID_2 … #define mmDCORE0_RTR0_CTRL_RGL_SRAM_BANK_ID_3 … #define mmDCORE0_RTR0_CTRL_RGL_SRAM_BANK_ID_4 … #define mmDCORE0_RTR0_CTRL_RGL_SRAM_BANK_ID_5 … #define mmDCORE0_RTR0_CTRL_RGL_SRAM_BANK_ID_6 … #define mmDCORE0_RTR0_CTRL_RGL_SRAM_BANK_ID_7 … #define mmDCORE0_RTR0_CTRL_RGL_SRAM_BANK_ID_8 … #define mmDCORE0_RTR0_CTRL_RGL_SRAM_BANK_ID_9 … #define mmDCORE0_RTR0_CTRL_RGL_SRAM_BANK_ID_10 … #define mmDCORE0_RTR0_CTRL_RGL_SRAM_BANK_ID_11 … #define mmDCORE0_RTR0_CTRL_RGL_SRAM_BANK_ID_12 … #define mmDCORE0_RTR0_CTRL_RGL_SRAM_BANK_ID_13 … #define mmDCORE0_RTR0_CTRL_RGL_SRAM_BANK_ID_14 … #define mmDCORE0_RTR0_CTRL_RGL_SRAM_BANK_ID_15 … #define mmDCORE0_RTR0_CTRL_RGL_SRAM_WDT_0 … #define mmDCORE0_RTR0_CTRL_RGL_SRAM_WDT_1 … #define mmDCORE0_RTR0_CTRL_RGL_SRAM_DEC_TOKEN_0 … #define mmDCORE0_RTR0_CTRL_RGL_SRAM_DEC_TOKEN_1 … #define mmDCORE0_RTR0_CTRL_DEC_RAZWI_HBW_AW_HI_ADDR … #define mmDCORE0_RTR0_CTRL_DEC_RAZWI_HBW_AW_LO_ADDR … #define mmDCORE0_RTR0_CTRL_DEC_RAZWI_HBW_AW_SET … #define mmDCORE0_RTR0_CTRL_DEC_RAZWI_HBW_AR_HI_ADDR … #define mmDCORE0_RTR0_CTRL_DEC_RAZWI_HBW_AR_LO_ADDR … #define mmDCORE0_RTR0_CTRL_DEC_RAZWI_HBW_AR_SET … #define mmDCORE0_RTR0_CTRL_DEC_RAZWI_LBW_AW_ADDR … #define mmDCORE0_RTR0_CTRL_DEC_RAZWI_LBW_AW_SET … #define mmDCORE0_RTR0_CTRL_DEC_RAZWI_LBW_AR_ADDR … #define mmDCORE0_RTR0_CTRL_DEC_RAZWI_LBW_AR_SET … #define mmDCORE0_RTR0_CTRL_RGL_MEM_CFG_0 … #define mmDCORE0_RTR0_CTRL_RGL_MEM_CFG_1 … #define mmDCORE0_RTR0_CTRL_RGL_MEM_SHIFT_0 … #define mmDCORE0_RTR0_CTRL_RGL_MEM_SHIFT_1 … #define mmDCORE0_RTR0_CTRL_RGL_MEM_EXPECTED_LAT_0 … #define mmDCORE0_RTR0_CTRL_RGL_MEM_EXPECTED_LAT_1 … #define mmDCORE0_RTR0_CTRL_RGL_MEM_EXPECTED_LAT_2 … #define mmDCORE0_RTR0_CTRL_RGL_MEM_EXPECTED_LAT_3 … #define mmDCORE0_RTR0_CTRL_RGL_MEM_EXPECTED_LAT_4 … #define mmDCORE0_RTR0_CTRL_RGL_MEM_EXPECTED_LAT_5 … #define mmDCORE0_RTR0_CTRL_RGL_MEM_EXPECTED_LAT_6 … #define mmDCORE0_RTR0_CTRL_RGL_MEM_EXPECTED_LAT_7 … #define mmDCORE0_RTR0_CTRL_RGL_MEM_EXPECTED_LAT_8 … #define mmDCORE0_RTR0_CTRL_RGL_MEM_EXPECTED_LAT_9 … #define mmDCORE0_RTR0_CTRL_RGL_MEM_EXPECTED_LAT_10 … #define mmDCORE0_RTR0_CTRL_RGL_MEM_EXPECTED_LAT_11 … #define mmDCORE0_RTR0_CTRL_RGL_MEM_EXPECTED_LAT_12 … #define mmDCORE0_RTR0_CTRL_RGL_MEM_EXPECTED_LAT_13 … #define mmDCORE0_RTR0_CTRL_RGL_MEM_EXPECTED_LAT_14 … #define mmDCORE0_RTR0_CTRL_RGL_MEM_EXPECTED_LAT_15 … #define mmDCORE0_RTR0_CTRL_RGL_MEM_TOKEN_0 … #define mmDCORE0_RTR0_CTRL_RGL_MEM_TOKEN_1 … #define mmDCORE0_RTR0_CTRL_RGL_MEM_TOKEN_2 … #define mmDCORE0_RTR0_CTRL_RGL_MEM_TOKEN_3 … #define mmDCORE0_RTR0_CTRL_RGL_MEM_TOKEN_4 … #define mmDCORE0_RTR0_CTRL_RGL_MEM_TOKEN_5 … #define mmDCORE0_RTR0_CTRL_RGL_MEM_TOKEN_6 … #define mmDCORE0_RTR0_CTRL_RGL_MEM_TOKEN_7 … #define mmDCORE0_RTR0_CTRL_RGL_MEM_TOKEN_8 … #define mmDCORE0_RTR0_CTRL_RGL_MEM_TOKEN_9 … #define mmDCORE0_RTR0_CTRL_RGL_MEM_TOKEN_10 … #define mmDCORE0_RTR0_CTRL_RGL_MEM_TOKEN_11 … #define mmDCORE0_RTR0_CTRL_RGL_MEM_TOKEN_12 … #define mmDCORE0_RTR0_CTRL_RGL_MEM_TOKEN_13 … #define mmDCORE0_RTR0_CTRL_RGL_MEM_TOKEN_14 … #define mmDCORE0_RTR0_CTRL_RGL_MEM_TOKEN_15 … #define mmDCORE0_RTR0_CTRL_RGL_MEM_ID_0 … #define mmDCORE0_RTR0_CTRL_RGL_MEM_ID_1 … #define mmDCORE0_RTR0_CTRL_RGL_MEM_ID_2 … #define mmDCORE0_RTR0_CTRL_RGL_MEM_ID_3 … #define mmDCORE0_RTR0_CTRL_RGL_MEM_ID_4 … #define mmDCORE0_RTR0_CTRL_RGL_MEM_ID_5 … #define mmDCORE0_RTR0_CTRL_RGL_MEM_ID_6 … #define mmDCORE0_RTR0_CTRL_RGL_MEM_ID_7 … #define mmDCORE0_RTR0_CTRL_RGL_MEM_ID_8 … #define mmDCORE0_RTR0_CTRL_RGL_MEM_ID_9 … #define mmDCORE0_RTR0_CTRL_RGL_MEM_ID_10 … #define mmDCORE0_RTR0_CTRL_RGL_MEM_ID_11 … #define mmDCORE0_RTR0_CTRL_RGL_MEM_ID_12 … #define mmDCORE0_RTR0_CTRL_RGL_MEM_ID_13 … #define mmDCORE0_RTR0_CTRL_RGL_MEM_ID_14 … #define mmDCORE0_RTR0_CTRL_RGL_MEM_ID_15 … #define mmDCORE0_RTR0_CTRL_RGL_MEM_WDT_0 … #define mmDCORE0_RTR0_CTRL_RGL_MEM_WDT_1 … #define mmDCORE0_RTR0_CTRL_RGL_WR_RED_CNT … #define mmDCORE0_RTR0_CTRL_RGL_MEM_DEC_TOKEN_0 … #define mmDCORE0_RTR0_CTRL_RGL_MEM_DEC_TOKEN_1 … #endif /* ASIC_REG_DCORE0_RTR0_CTRL_REGS_H_ */
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