#ifndef ASIC_REG_DCORE0_DEC0_CMD_REGS_H_
#define ASIC_REG_DCORE0_DEC0_CMD_REGS_H_
#define mmDCORE0_DEC0_CMD_SWREG0 …
#define mmDCORE0_DEC0_CMD_SWREG1 …
#define mmDCORE0_DEC0_CMD_SWREG2 …
#define mmDCORE0_DEC0_CMD_SWREG3 …
#define mmDCORE0_DEC0_CMD_SWREG4 …
#define mmDCORE0_DEC0_CMD_SWREG5 …
#define mmDCORE0_DEC0_CMD_SWREG6 …
#define mmDCORE0_DEC0_CMD_SWREG7 …
#define mmDCORE0_DEC0_CMD_SWREG8 …
#define mmDCORE0_DEC0_CMD_SWREG9 …
#define mmDCORE0_DEC0_CMD_SWREG10 …
#define mmDCORE0_DEC0_CMD_SWREG11 …
#define mmDCORE0_DEC0_CMD_SWREG12 …
#define mmDCORE0_DEC0_CMD_SWREG13 …
#define mmDCORE0_DEC0_CMD_SWREG14 …
#define mmDCORE0_DEC0_CMD_SWREG15 …
#define mmDCORE0_DEC0_CMD_SWREG16 …
#define mmDCORE0_DEC0_CMD_SWREG17 …
#define mmDCORE0_DEC0_CMD_SWREG18 …
#define mmDCORE0_DEC0_CMD_SWREG19 …
#define mmDCORE0_DEC0_CMD_SWREG20 …
#define mmDCORE0_DEC0_CMD_SWREG21 …
#define mmDCORE0_DEC0_CMD_SWREG22 …
#define mmDCORE0_DEC0_CMD_SWREG23 …
#define mmDCORE0_DEC0_CMD_SWREG24 …
#define mmDCORE0_DEC0_CMD_SWREG25 …
#define mmDCORE0_DEC0_CMD_SWREG26 …
#define mmDCORE0_DEC0_CMD_SWREG64 …
#define mmDCORE0_DEC0_CMD_SWREG65 …
#define mmDCORE0_DEC0_CMD_SWREG66 …
#define mmDCORE0_DEC0_CMD_SWREG67 …
#endif