/* SPDX-License-Identifier: GPL-2.0 * * Copyright 2016-2020 HabanaLabs, Ltd. * All Rights Reserved. * */ /************************************ ** This is an auto-generated file ** ** DO NOT EDIT BELOW ** ************************************/ #ifndef ASIC_REG_DCORE0_VDEC0_BRDG_CTRL_REGS_H_ #define ASIC_REG_DCORE0_VDEC0_BRDG_CTRL_REGS_H_ /* ***************************************** * DCORE0_VDEC0_BRDG_CTRL * (Prototype: VDEC_BRDG_CTRL) ***************************************** */ #define mmDCORE0_VDEC0_BRDG_CTRL_CGM_DISABLE … #define mmDCORE0_VDEC0_BRDG_CTRL_IDLE_MASK … #define mmDCORE0_VDEC0_BRDG_CTRL_APB_CGM_CNT … #define mmDCORE0_VDEC0_BRDG_CTRL_APB_ARB_WDOG_CNT … #define mmDCORE0_VDEC0_BRDG_CTRL_GRACEFUL … #define mmDCORE0_VDEC0_BRDG_CTRL_IDLE_CGM_CNT … #define mmDCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR … #define mmDCORE0_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_CAUSE … #define mmDCORE0_VDEC0_BRDG_CTRL_LBW_AXI_VIOL_CAUSE … #define mmDCORE0_VDEC0_BRDG_CTRL_AXI_VIOL_CLR_STICKY_TERM … #define mmDCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_MASK … #define mmDCORE0_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_MASK … #define mmDCORE0_VDEC0_BRDG_CTRL_LBW_AXI_VIOL_MASK … #define mmDCORE0_VDEC0_BRDG_CTRL_VCD_GIC_INTR_MASK … #define mmDCORE0_VDEC0_BRDG_CTRL_L2C_GIC_INTR_MASK … #define mmDCORE0_VDEC0_BRDG_CTRL_NRM_GIC_INTR_MASK … #define mmDCORE0_VDEC0_BRDG_CTRL_ABNRM_GIC_INTR_MASK … #define mmDCORE0_VDEC0_BRDG_CTRL_DEC_HBW_AWPROT … #define mmDCORE0_VDEC0_BRDG_CTRL_DEC_HBW_ARPROT … #define mmDCORE0_VDEC0_BRDG_CTRL_DEC_LBW_AWPROT … #define mmDCORE0_VDEC0_BRDG_CTRL_DEC_LBW_ARPROT … #define mmDCORE0_VDEC0_BRDG_CTRL_DEC_LBW_SLV_AWPROT … #define mmDCORE0_VDEC0_BRDG_CTRL_DEC_LBW_SLV_ARPROT … #define mmDCORE0_VDEC0_BRDG_CTRL_DEC_AXI_LEGAL_AXSIZE … #define mmDCORE0_VDEC0_BRDG_CTRL_ARC_MSG_MASK … #define mmDCORE0_VDEC0_BRDG_CTRL_ARC_START_LBW_WDATA … #define mmDCORE0_VDEC0_BRDG_CTRL_ARC_FINISH_LBW_WDATA … #define mmDCORE0_VDEC0_BRDG_CTRL_HWEVENT_TRACE_SEL … #define mmDCORE0_VDEC0_BRDG_CTRL_HWEVENT_TRACE_ADDR … #define mmDCORE0_VDEC0_BRDG_CTRL_DEC_FREE_RUN_CNT_L … #define mmDCORE0_VDEC0_BRDG_CTRL_DEC_FREE_RUN_CNT_H … #define mmDCORE0_VDEC0_BRDG_CTRL_DEC_FREE_RUN_SET_VALUE_L … #define mmDCORE0_VDEC0_BRDG_CTRL_DEC_FREE_RUN_SET_VALUE_H … #define mmDCORE0_VDEC0_BRDG_CTRL_DEC_BUSY_CNT_L … #define mmDCORE0_VDEC0_BRDG_CTRL_DEC_BUSY_CNT_H … #define mmDCORE0_VDEC0_BRDG_CTRL_DEC_BUSY_SET_VALUE_L … #define mmDCORE0_VDEC0_BRDG_CTRL_DEC_BUSY_SET_VALUE_H … #define mmDCORE0_VDEC0_BRDG_CTRL_STAT_CNTR_EN … #define mmDCORE0_VDEC0_BRDG_CTRL_VCD_INTR_MASK … #define mmDCORE0_VDEC0_BRDG_CTRL_VCD_MSIX_FLOW_MASK … #define mmDCORE0_VDEC0_BRDG_CTRL_VCD_WAIT_CNTR … #define mmDCORE0_VDEC0_BRDG_CTRL_VCD_MSIX_WAIT_CNTR … #define mmDCORE0_VDEC0_BRDG_CTRL_STAT_VCD_WAIT_CNTR … #define mmDCORE0_VDEC0_BRDG_CTRL_STAT_VCD_MSIX_WAIT_CNTR … #define mmDCORE0_VDEC0_BRDG_CTRL_VCD_SWREG1_ADDR … #define mmDCORE0_VDEC0_BRDG_CTRL_VCD_APB_WR_ADDR … #define mmDCORE0_VDEC0_BRDG_CTRL_VCD_APB_WR_DATA … #define mmDCORE0_VDEC0_BRDG_CTRL_VCD_CPLQ_HBW_AWPROT … #define mmDCORE0_VDEC0_BRDG_CTRL_VCD_CPLQ_HBW_AWADDR_L … #define mmDCORE0_VDEC0_BRDG_CTRL_VCD_CPLQ_HBW_AWADDR_H … #define mmDCORE0_VDEC0_BRDG_CTRL_VCD_MSIX_LBW_AWPROT … #define mmDCORE0_VDEC0_BRDG_CTRL_VCD_MSIX_LBW_AWADDR … #define mmDCORE0_VDEC0_BRDG_CTRL_VCD_MSIX_LBW_WDATA … #define mmDCORE0_VDEC0_BRDG_CTRL_L2C_INTR_MASK … #define mmDCORE0_VDEC0_BRDG_CTRL_L2C_MSIX_FLOW_MASK … #define mmDCORE0_VDEC0_BRDG_CTRL_L2C_WAIT_CNTR … #define mmDCORE0_VDEC0_BRDG_CTRL_L2C_MSIX_WAIT_CNTR … #define mmDCORE0_VDEC0_BRDG_CTRL_STAT_L2C_WAIT_CNTR … #define mmDCORE0_VDEC0_BRDG_CTRL_STAT_L2C_MSIX_WAIT_CNTR … #define mmDCORE0_VDEC0_BRDG_CTRL_L2C_SWREG1_ADDR … #define mmDCORE0_VDEC0_BRDG_CTRL_L2C_APB_WR_ADDR … #define mmDCORE0_VDEC0_BRDG_CTRL_L2C_APB_WR_DATA … #define mmDCORE0_VDEC0_BRDG_CTRL_L2C_CPLQ_HBW_AWPROT … #define mmDCORE0_VDEC0_BRDG_CTRL_L2C_CPLQ_HBW_AWADDR_L … #define mmDCORE0_VDEC0_BRDG_CTRL_L2C_CPLQ_HBW_AWADDR_H … #define mmDCORE0_VDEC0_BRDG_CTRL_L2C_MSIX_LBW_AWPROT … #define mmDCORE0_VDEC0_BRDG_CTRL_L2C_MSIX_LBW_AWADDR … #define mmDCORE0_VDEC0_BRDG_CTRL_L2C_MSIX_LBW_WDATA … #define mmDCORE0_VDEC0_BRDG_CTRL_NRM_INTR_MASK … #define mmDCORE0_VDEC0_BRDG_CTRL_NRM_MSIX_FLOW_MASK … #define mmDCORE0_VDEC0_BRDG_CTRL_NRM_WAIT_CNTR … #define mmDCORE0_VDEC0_BRDG_CTRL_NRM_MSIX_WAIT_CNTR … #define mmDCORE0_VDEC0_BRDG_CTRL_STAT_NRM_WAIT_CNTR … #define mmDCORE0_VDEC0_BRDG_CTRL_STAT_NRM_MSIX_WAIT_CNTR … #define mmDCORE0_VDEC0_BRDG_CTRL_NRM_SWREG1_ADDR … #define mmDCORE0_VDEC0_BRDG_CTRL_NRM_APB_WR_ADDR … #define mmDCORE0_VDEC0_BRDG_CTRL_NRM_APB_WR_DATA … #define mmDCORE0_VDEC0_BRDG_CTRL_NRM_CPLQ_HBW_AWPROT … #define mmDCORE0_VDEC0_BRDG_CTRL_NRM_CPLQ_HBW_AWADDR_L … #define mmDCORE0_VDEC0_BRDG_CTRL_NRM_CPLQ_HBW_AWADDR_H … #define mmDCORE0_VDEC0_BRDG_CTRL_NRM_MSIX_LBW_AWPROT … #define mmDCORE0_VDEC0_BRDG_CTRL_NRM_MSIX_LBW_AWADDR … #define mmDCORE0_VDEC0_BRDG_CTRL_NRM_MSIX_LBW_WDATA … #define mmDCORE0_VDEC0_BRDG_CTRL_ABNRM_INTR_MASK … #define mmDCORE0_VDEC0_BRDG_CTRL_ABNRM_MSIX_FLOW_MASK … #define mmDCORE0_VDEC0_BRDG_CTRL_ABNRM_WAIT_CNTR … #define mmDCORE0_VDEC0_BRDG_CTRL_ABNRM_MSIX_WAIT_CNTR … #define mmDCORE0_VDEC0_BRDG_CTRL_STAT_ABNRM_WAIT_CNTR … #define mmDCORE0_VDEC0_BRDG_CTRL_STAT_ABNRM_MSIX_WAIT_CNTR … #define mmDCORE0_VDEC0_BRDG_CTRL_ABNRM_SWREG1_ADDR … #define mmDCORE0_VDEC0_BRDG_CTRL_ABNRM_APB_WR_ADDR … #define mmDCORE0_VDEC0_BRDG_CTRL_ABNRM_APB_WR_DATA … #define mmDCORE0_VDEC0_BRDG_CTRL_ABNRM_CPLQ_HBW_AWPROT … #define mmDCORE0_VDEC0_BRDG_CTRL_ABNRM_CPLQ_HBW_AWADDR_L … #define mmDCORE0_VDEC0_BRDG_CTRL_ABNRM_CPLQ_HBW_AWADDR_H … #define mmDCORE0_VDEC0_BRDG_CTRL_ABNRM_MSIX_LBW_AWPROT … #define mmDCORE0_VDEC0_BRDG_CTRL_ABNRM_MSIX_LBW_AWADDR … #define mmDCORE0_VDEC0_BRDG_CTRL_ABNRM_MSIX_LBW_WDATA … #define mmDCORE0_VDEC0_BRDG_CTRL_AXI_SPLIT_BRESP_ERR_ID … #define mmDCORE0_VDEC0_BRDG_CTRL_AXI_SPLIT_CFG … #define mmDCORE0_VDEC0_BRDG_CTRL_AXI_SPLIT_NO_WR_INFLIGHT … #define mmDCORE0_VDEC0_BRDG_CTRL_HWEVENT_MASK … #define mmDCORE0_VDEC0_BRDG_CTRL_HWEVENT_CNTXT … #define mmDCORE0_VDEC0_BRDG_CTRL_LBW_SLV_TERM_ERR_RESP … #define mmDCORE0_VDEC0_BRDG_CTRL_LBW_MSTR_TERM_ERR_RESP … #define mmDCORE0_VDEC0_BRDG_CTRL_DEC_HBW_MSTR_ERR_RESP … #define mmDCORE0_VDEC0_BRDG_CTRL_HBW_VIOL_TERM_STATUS … #define mmDCORE0_VDEC0_BRDG_CTRL_HBW_LAST_AWADDR_TERM_L … #define mmDCORE0_VDEC0_BRDG_CTRL_HBW_LAST_AWADDR_TERM_H … #define mmDCORE0_VDEC0_BRDG_CTRL_HBW_LAST_ARADDR_TERM_L … #define mmDCORE0_VDEC0_BRDG_CTRL_HBW_LAST_ARADDR_TERM_H … #endif /* ASIC_REG_DCORE0_VDEC0_BRDG_CTRL_REGS_H_ */
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