#ifndef ASIC_REG_PCIE_VDEC0_BRDG_CTRL_AXUSER_DEC_REGS_H_
#define ASIC_REG_PCIE_VDEC0_BRDG_CTRL_AXUSER_DEC_REGS_H_
#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_DEC_HB_ASID …
#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_DEC_HB_MMU_BP …
#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_DEC_HB_STRONG_ORDER …
#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_DEC_HB_NO_SNOOP …
#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_DEC_HB_WR_REDUCTION …
#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_DEC_HB_RD_ATOMIC …
#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_DEC_HB_QOS …
#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_DEC_HB_RSVD …
#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_DEC_HB_EMEM_CPAGE …
#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_DEC_HB_CORE …
#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_DEC_E2E_COORD …
#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_DEC_HB_WR_OVRD_LO …
#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_DEC_HB_WR_OVRD_HI …
#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_DEC_HB_RD_OVRD_LO …
#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_DEC_HB_RD_OVRD_HI …
#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_DEC_LB_COORD …
#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_DEC_LB_LOCK …
#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_DEC_LB_RSVD …
#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_DEC_LB_OVRD …
#endif