/* SPDX-License-Identifier: GPL-2.0 * * Copyright 2016-2020 HabanaLabs, Ltd. * All Rights Reserved. * */ /************************************ ** This is an auto-generated file ** ** DO NOT EDIT BELOW ** ************************************/ #ifndef ASIC_REG_DCORE0_MME_QM_ARC_ACP_ENG_REGS_H_ #define ASIC_REG_DCORE0_MME_QM_ARC_ACP_ENG_REGS_H_ /* ***************************************** * DCORE0_MME_QM_ARC_ACP_ENG * (Prototype: ARC_ACP_ENG) ***************************************** */ #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_0 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_1 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_2 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_3 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_4 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_5 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_6 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_7 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_8 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_9 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_10 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_11 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_12 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_13 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_14 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_15 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_16 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_17 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_18 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_19 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_20 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_21 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_22 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_23 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_24 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_25 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_26 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_27 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_28 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_29 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_30 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_31 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_32 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_33 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_34 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_35 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_36 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_37 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_38 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_39 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_40 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_41 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_42 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_43 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_44 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_45 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_46 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_47 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_48 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_49 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_50 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_51 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_52 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_53 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_54 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_55 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_56 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_57 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_58 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_59 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_60 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_61 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_62 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_63 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_0 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_1 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_2 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_3 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_4 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_5 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_6 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_7 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_8 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_9 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_10 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_11 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_12 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_13 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_14 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_15 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_16 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_17 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_18 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_19 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_20 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_21 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_22 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_23 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_24 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_25 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_26 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_27 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_28 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_29 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_30 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_31 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_32 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_33 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_34 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_35 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_36 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_37 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_38 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_39 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_40 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_41 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_42 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_43 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_44 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_45 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_46 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_47 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_48 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_49 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_50 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_51 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_52 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_53 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_54 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_55 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_56 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_57 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_58 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_59 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_60 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_61 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_62 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_CI_REG_63 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_0 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_1 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_2 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_3 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_4 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_5 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_6 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_7 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_8 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_9 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_10 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_11 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_12 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_13 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_14 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_15 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_16 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_17 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_18 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_19 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_20 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_21 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_22 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_23 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_24 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_25 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_26 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_27 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_28 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_29 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_30 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_31 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_32 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_33 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_34 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_35 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_36 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_37 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_38 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_39 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_40 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_41 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_42 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_43 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_44 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_45 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_46 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_47 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_48 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_49 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_50 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_51 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_52 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_53 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_54 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_55 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_56 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_57 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_58 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_59 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_60 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_61 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_62 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PR_REG_63 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_0 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_1 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_2 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_3 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_4 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_5 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_6 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_7 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_8 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_9 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_10 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_11 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_12 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_13 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_14 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_15 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_16 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_17 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_18 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_19 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_20 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_21 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_22 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_23 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_24 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_25 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_26 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_27 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_28 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_29 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_30 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_31 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_32 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_33 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_34 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_35 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_36 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_37 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_38 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_39 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_40 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_41 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_42 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_43 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_44 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_45 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_46 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_47 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_48 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_49 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_50 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_51 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_52 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_53 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_54 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_55 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_56 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_57 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_58 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_59 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_60 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_61 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_62 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_MK_REG_63 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_SELECTED_QUEUE_ID … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_GRANTS_WEIGHT_PRIO_0 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_GRANTS_WEIGHT_PRIO_1 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_GRANTS_WEIGHT_PRIO_2 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_GRANTS_COUNTER_PRIO_0 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_GRANTS_COUNTER_PRIO_1 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_GRANTS_COUNTER_PRIO_2 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_DBG_PRIO_OUT_CNT_0 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_DBG_PRIO_OUT_CNT_1 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_DBG_PRIO_OUT_CNT_2 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_DBG_PRIO_OUT_CNT_3 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_DBG_PRIO_RD_CNT_0 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_DBG_PRIO_RD_CNT_1 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_DBG_PRIO_RD_CNT_2 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_DBG_PRIO_RD_CNT_3 … #define mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_DBG_REG … #endif /* ASIC_REG_DCORE0_MME_QM_ARC_ACP_ENG_REGS_H_ */
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