/* SPDX-License-Identifier: GPL-2.0 * * Copyright 2016-2020 HabanaLabs, Ltd. * All Rights Reserved. * */ /************************************ ** This is an auto-generated file ** ** DO NOT EDIT BELOW ** ************************************/ #ifndef ASIC_REG_DCORE0_MME_QM_ARC_DUP_ENG_REGS_H_ #define ASIC_REG_DCORE0_MME_QM_ARC_DUP_ENG_REGS_H_ /* ***************************************** * DCORE0_MME_QM_ARC_DUP_ENG * (Prototype: ARC_DUP_ENG) ***************************************** */ #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TPC_ENG_ADDR_0 … #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TPC_ENG_ADDR_1 … #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TPC_ENG_ADDR_2 … #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TPC_ENG_ADDR_3 … #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TPC_ENG_ADDR_4 … #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TPC_ENG_ADDR_5 … #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TPC_ENG_ADDR_6 … #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TPC_ENG_ADDR_7 … #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TPC_ENG_ADDR_8 … #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TPC_ENG_ADDR_9 … #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TPC_ENG_ADDR_10 … #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TPC_ENG_ADDR_11 … #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TPC_ENG_ADDR_12 … #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TPC_ENG_ADDR_13 … #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TPC_ENG_ADDR_14 … #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TPC_ENG_ADDR_15 … #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TPC_ENG_ADDR_16 … #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TPC_ENG_ADDR_17 … #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TPC_ENG_ADDR_18 … #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TPC_ENG_ADDR_19 … #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TPC_ENG_ADDR_20 … #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TPC_ENG_ADDR_21 … #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TPC_ENG_ADDR_22 … #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TPC_ENG_ADDR_23 … #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TPC_ENG_ADDR_24 … #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_MME_ENG_ADDR_0 … #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_MME_ENG_ADDR_1 … #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_MME_ENG_ADDR_2 … #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_MME_ENG_ADDR_3 … #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_NIC_ENG_ADDR_0 … #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_NIC_ENG_ADDR_1 … #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_NIC_ENG_ADDR_2 … #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_NIC_ENG_ADDR_3 … #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_NIC_ENG_ADDR_4 … #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_NIC_ENG_ADDR_5 … #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_NIC_ENG_ADDR_6 … #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_NIC_ENG_ADDR_7 … #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_NIC_ENG_ADDR_8 … #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_NIC_ENG_ADDR_9 … #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_NIC_ENG_ADDR_10 … #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_NIC_ENG_ADDR_11 … #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_NIC_ENG_ADDR_12 … #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_NIC_ENG_ADDR_13 … #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_NIC_ENG_ADDR_14 … #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_NIC_ENG_ADDR_15 … #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_NIC_ENG_ADDR_16 … #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_NIC_ENG_ADDR_17 … #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_NIC_ENG_ADDR_18 … #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_NIC_ENG_ADDR_19 … #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_NIC_ENG_ADDR_20 … #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_NIC_ENG_ADDR_21 … #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_NIC_ENG_ADDR_22 … #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_NIC_ENG_ADDR_23 … #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_EDMA_ENG_ADDR_0 … #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_EDMA_ENG_ADDR_1 … #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_EDMA_ENG_ADDR_2 … #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_EDMA_ENG_ADDR_3 … #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_EDMA_ENG_ADDR_4 … #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_EDMA_ENG_ADDR_5 … #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_EDMA_ENG_ADDR_6 … #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_EDMA_ENG_ADDR_7 … #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_PDMA_ENG_ADDR_0 … #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_PDMA_ENG_ADDR_1 … #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_ROT_ENG_ADDR_0 … #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_ROT_ENG_ADDR_1 … #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_RSVD_ENG_ADDR_0 … #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_RSVD_ENG_ADDR_1 … #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_RSVD_ENG_ADDR_2 … #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_RSVD_ENG_ADDR_3 … #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_RSVD_ENG_ADDR_4 … #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_RSVD_ENG_ADDR_5 … #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_RSVD_ENG_ADDR_6 … #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_RSVD_ENG_ADDR_7 … #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_RSVD_ENG_ADDR_8 … #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_RSVD_ENG_ADDR_9 … #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_RSVD_ENG_ADDR_10 … #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_RSVD_ENG_ADDR_11 … #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_RSVD_ENG_ADDR_12 … #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_RSVD_ENG_ADDR_13 … #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_RSVD_ENG_ADDR_14 … #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_RSVD_ENG_ADDR_15 … #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TPC_ENG_MASK … #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_MME_ENG_MASK … #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_EDMA_ENG_MASK … #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_PDMA_ENG_MASK … #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_ROT_ENG_MASK … #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_RSVD_ENG_MASK … #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_NIC_ENG_MASK_0 … #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_NIC_ENG_MASK_1 … #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_NIC_ENG_MASK_2 … #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_NIC_ENG_MASK_3 … #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_NIC_ENG_MASK_4 … #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_NIC_ENG_MASK_5 … #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_NIC_ENG_MASK_6 … #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_NIC_ENG_MASK_7 … #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TRANS_DATA_Q_0_0 … #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TRANS_DATA_Q_0_1 … #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TRANS_DATA_Q_0_2 … #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TRANS_DATA_Q_0_3 … #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TRANS_DATA_Q_0_4 … #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TRANS_DATA_Q_0_5 … #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TRANS_DATA_Q_0_6 … #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TRANS_DATA_Q_0_7 … #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TRANS_DATA_Q_0_8 … #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TRANS_DATA_Q_0_9 … #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TRANS_DATA_Q_0_10 … #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TRANS_DATA_Q_0_11 … #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TRANS_DATA_Q_0_12 … #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TRANS_DATA_Q_0_13 … #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TRANS_DATA_Q_1_0 … #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TRANS_DATA_Q_1_1 … #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TRANS_DATA_Q_1_2 … #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TRANS_DATA_Q_1_3 … #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TRANS_DATA_Q_1_4 … #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TRANS_DATA_Q_1_5 … #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TRANS_DATA_Q_2_0 … #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TRANS_DATA_Q_2_1 … #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TRANS_DATA_Q_2_2 … #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TRANS_DATA_Q_2_3 … #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TRANS_DATA_Q_2_4 … #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TRANS_DATA_Q_2_5 … #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TRANS_DATA_Q_3_0 … #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TRANS_DATA_Q_3_1 … #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TRANS_DATA_Q_3_2 … #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TRANS_DATA_Q_3_3 … #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TRANS_DATA_Q_3_4 … #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TRANS_DATA_Q_3_5 … #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_GENERAL_CFG … #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_BP_CFG … #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_GRP_ENG_ADDR_OFFSET_0 … #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_GRP_ENG_ADDR_OFFSET_1 … #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_GRP_ENG_ADDR_OFFSET_2 … #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_GRP_ENG_ADDR_OFFSET_3 … #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_GRP_ENG_ADDR_OFFSET_4 … #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_GRP_ENG_ADDR_OFFSET_5 … #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_GRP_ENG_ADDR_OFFSET_6 … #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_GRP_ENG_ADDR_OFFSET_7 … #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_GRP_ENG_ADDR_OFFSET_8 … #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_GRP_ENG_ADDR_OFFSET_9 … #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_GRP_ENG_ADDR_OFFSET_10 … #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_GRP_ENG_ADDR_OFFSET_11 … #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_GRP_ENG_ADDR_OFFSET_12 … #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_GRP_ENG_ADDR_OFFSET_13 … #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_DBG_IN_GRP_TRANS_0 … #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_DBG_IN_GRP_TRANS_1 … #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_DBG_IN_GRP_TRANS_2 … #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_DBG_STS … #define mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_DBG_OUT_RQ_CNT … #define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_0 … #define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_1 … #define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_2 … #define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_3 … #define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_4 … #define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_5 … #define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_6 … #define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_7 … #define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_8 … #define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_9 … #define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_10 … #define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_11 … #define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_12 … #define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_13 … #define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_14 … #define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_15 … #define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_16 … #define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_17 … #define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_18 … #define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_19 … #define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_20 … #define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_21 … #define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_22 … #define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_23 … #define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_24 … #define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_25 … #define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_26 … #define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_27 … #define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_28 … #define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_29 … #define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_30 … #define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_31 … #define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_32 … #define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_33 … #define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_34 … #define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_35 … #define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_36 … #define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_37 … #define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_38 … #define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_39 … #define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_40 … #define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_41 … #define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_42 … #define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_43 … #define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_44 … #define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_45 … #define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_46 … #define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_47 … #define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_48 … #define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_49 … #define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_50 … #define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_51 … #define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_52 … #define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_53 … #define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_54 … #define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_55 … #define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_56 … #define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_57 … #define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_58 … #define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_59 … #define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_60 … #define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_61 … #define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_62 … #define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CONTEXT_ID_63 … #define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_0 … #define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_1 … #define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_2 … #define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_3 … #define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_4 … #define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_5 … #define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_6 … #define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_7 … #define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_8 … #define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_9 … #define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_10 … #define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_11 … #define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_12 … #define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_13 … #define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_14 … #define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_15 … #define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_16 … #define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_17 … #define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_18 … #define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_19 … #define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_20 … #define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_21 … #define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_22 … #define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_23 … #define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_24 … #define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_25 … #define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_26 … #define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_27 … #define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_28 … #define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_29 … #define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_30 … #define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_31 … #define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_32 … #define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_33 … #define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_34 … #define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_35 … #define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_36 … #define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_37 … #define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_38 … #define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_39 … #define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_40 … #define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_41 … #define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_42 … #define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_43 … #define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_44 … #define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_45 … #define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_46 … #define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_47 … #define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_48 … #define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_49 … #define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_50 … #define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_51 … #define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_52 … #define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_53 … #define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_54 … #define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_55 … #define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_56 … #define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_57 … #define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_58 … #define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_59 … #define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_60 … #define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_61 … #define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_62 … #define mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_63 … #endif /* ASIC_REG_DCORE0_MME_QM_ARC_DUP_ENG_REGS_H_ */
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