#ifndef ASIC_REG_DCORE0_MME_ACC_REGS_H_
#define ASIC_REG_DCORE0_MME_ACC_REGS_H_
#define mmDCORE0_MME_ACC_WBC0_AXI …
#define mmDCORE0_MME_ACC_WBC1_AXI …
#define mmDCORE0_MME_ACC_WBC0_RL …
#define mmDCORE0_MME_ACC_WBC1_RL …
#define mmDCORE0_MME_ACC_WBC_STALL …
#define mmDCORE0_MME_ACC_AWCACHE …
#define mmDCORE0_MME_ACC_AWPROT …
#define mmDCORE0_MME_ACC_AP_LFSR_POLY …
#define mmDCORE0_MME_ACC_AP_LFSR_SEED_WDATA …
#define mmDCORE0_MME_ACC_AP_LFSR_SEED_SEL …
#define mmDCORE0_MME_ACC_AP_LFSR_SEED_RDATA …
#define mmDCORE0_MME_ACC_AP_LFSR_CLOSE_CGATE_DLY …
#define mmDCORE0_MME_ACC_WBC_SRC_BP …
#define mmDCORE0_MME_ACC_CLK_GATE_EN …
#define mmDCORE0_MME_ACC_WBC_INFLIGHTS …
#define mmDCORE0_MME_ACC_HBW_CLK_ENABLER_DIS …
#define mmDCORE0_MME_ACC_E2E_CRDT_TOP0 …
#define mmDCORE0_MME_ACC_E2E_CRDT_TOP1 …
#define mmDCORE0_MME_ACC_INTR_CAUSE …
#define mmDCORE0_MME_ACC_INTR_MASK …
#define mmDCORE0_MME_ACC_INTR_CLEAR …
#define mmDCORE0_MME_ACC_WR_AXI_AGG_COUT0 …
#define mmDCORE0_MME_ACC_WR_AXI_AGG_COUT1 …
#define mmDCORE0_MME_ACC_BIST …
#define mmDCORE0_MME_ACC_WR_AXI_AGG_2P_BVALID …
#endif