/* SPDX-License-Identifier: GPL-2.0 * * Copyright 2016-2020 HabanaLabs, Ltd. * All Rights Reserved. * */ /************************************ ** This is an auto-generated file ** ** DO NOT EDIT BELOW ** ************************************/ #ifndef ASIC_REG_DCORE0_MME_CTRL_LO_REGS_H_ #define ASIC_REG_DCORE0_MME_CTRL_LO_REGS_H_ /* ***************************************** * DCORE0_MME_CTRL_LO * (Prototype: MME_CTRL_LO) ***************************************** */ #define mmDCORE0_MME_CTRL_LO_ARCH_STATUS … #define mmDCORE0_MME_CTRL_LO_CMD … #define mmDCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_DW0 … #define mmDCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_ADDR0 … #define mmDCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_VAL0 … #define mmDCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_ADDR1 … #define mmDCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_VAL1 … #define mmDCORE0_MME_CTRL_LO_ARCH_A_SS … #define mmDCORE0_MME_CTRL_LO_ARCH_B_SS … #define mmDCORE0_MME_CTRL_LO_ARCH_COUT_SS … #define mmDCORE0_MME_CTRL_LO_QM_STALL … #define mmDCORE0_MME_CTRL_LO_LOG_SHADOW_LO … #define mmDCORE0_MME_CTRL_LO_LOG_SHADOW_HI … #define mmDCORE0_MME_CTRL_LO_SYNC_OBJECT_FIFO_TH … #define mmDCORE0_MME_CTRL_LO_REDUN … #define mmDCORE0_MME_CTRL_LO_EUS_LOCAL_FIFO_TH … #define mmDCORE0_MME_CTRL_LO_EUS_ROLLUP_DLY_DW0 … #define mmDCORE0_MME_CTRL_LO_EUS_ROLLUP_DLY_DW1 … #define mmDCORE0_MME_CTRL_LO_EUS_ROLLUP_CD_PROT_F16 … #define mmDCORE0_MME_CTRL_LO_EUS_ROLLUP_CD_PROT_F8 … #define mmDCORE0_MME_CTRL_LO_EUS_ROLLUP_CD_PROT_FP32 … #define mmDCORE0_MME_CTRL_LO_EUS_ROLLUP_CD_PROT_FP32I … #define mmDCORE0_MME_CTRL_LO_EUS_ROLLUP_CD_PROT_TF32 … #define mmDCORE0_MME_CTRL_LO_PCU_RL_DESC0 … #define mmDCORE0_MME_CTRL_LO_PCU_RL_TOKEN_UPDATE … #define mmDCORE0_MME_CTRL_LO_PCU_RL_TH … #define mmDCORE0_MME_CTRL_LO_PCU_RL_MIN … #define mmDCORE0_MME_CTRL_LO_PCU_RL_CTRL_EN … #define mmDCORE0_MME_CTRL_LO_PCU_RL_HISTORY_LOG_SIZE … #define mmDCORE0_MME_CTRL_LO_PCU_DUMMY_A_BF16 … #define mmDCORE0_MME_CTRL_LO_PCU_DUMMY_B_BF16 … #define mmDCORE0_MME_CTRL_LO_PCU_DUMMY_A_FP16 … #define mmDCORE0_MME_CTRL_LO_PCU_DUMMY_B_FP16 … #define mmDCORE0_MME_CTRL_LO_PCU_DUMMY_F8 … #define mmDCORE0_MME_CTRL_LO_PCU_DUMMY_A_FP32_ODD … #define mmDCORE0_MME_CTRL_LO_PCU_DUMMY_A_FP32_EVEN … #define mmDCORE0_MME_CTRL_LO_PCU_DUMMY_B_FP32_ODD … #define mmDCORE0_MME_CTRL_LO_PCU_DUMMY_B_FP32_EVEN … #define mmDCORE0_MME_CTRL_LO_PCU_DUMMY_A_TF32_ODD … #define mmDCORE0_MME_CTRL_LO_PCU_DUMMY_A_TF32_EVEN … #define mmDCORE0_MME_CTRL_LO_PCU_DUMMY_B_TF32_ODD … #define mmDCORE0_MME_CTRL_LO_PCU_DUMMY_B_TF32_EVEN … #define mmDCORE0_MME_CTRL_LO_PROT … #define mmDCORE0_MME_CTRL_LO_EU … #define mmDCORE0_MME_CTRL_LO_SBTE … #define mmDCORE0_MME_CTRL_LO_AGU_SM_INFLIGHT_CNTR … #define mmDCORE0_MME_CTRL_LO_AGU_SM_TOTAL_CNTR … #define mmDCORE0_MME_CTRL_LO_PCU_RL_SAT_SEC … #define mmDCORE0_MME_CTRL_LO_FMA_FUNC_REDUN_CLK_EN32 … #define mmDCORE0_MME_CTRL_LO_FMA_FUNC_REDUN_CLK_EN33 … #define mmDCORE0_MME_CTRL_LO_EU_ISOLATION_DIS … #define mmDCORE0_MME_CTRL_LO_QM_SLV_CLK_EN … #define mmDCORE0_MME_CTRL_LO_HBW_CLK_ENABLER_DIS … #define mmDCORE0_MME_CTRL_LO_AGU … #define mmDCORE0_MME_CTRL_LO_QM … #define mmDCORE0_MME_CTRL_LO_EARLY_RELEASE_STATUS … #define mmDCORE0_MME_CTRL_LO_INTR_CAUSE … #define mmDCORE0_MME_CTRL_LO_INTR_MASK … #define mmDCORE0_MME_CTRL_LO_INTR_CLEAR … #define mmDCORE0_MME_CTRL_LO_REDUN_PSOC_SEL_SEC … #define mmDCORE0_MME_CTRL_LO_BIST … #define mmDCORE0_MME_CTRL_LO_EU_RL_ENABLE … #define mmDCORE0_MME_CTRL_LO_EU_RL_TOKEN_SEL … #define mmDCORE0_MME_CTRL_LO_EU_RL_CFG … #define mmDCORE0_MME_CTRL_LO_PCU_DBG_DW0 … #define mmDCORE0_MME_CTRL_LO_PCU_DBG_DW1 … #define mmDCORE0_MME_CTRL_LO_PCU_DBG_DW2 … #define mmDCORE0_MME_CTRL_LO_PCU_DBG_DW3 … #define mmDCORE0_MME_CTRL_LO_PCU_DBG_WKL_ID … #define mmDCORE0_MME_CTRL_LO_ETF_MEM_WRAP_RM … #endif /* ASIC_REG_DCORE0_MME_CTRL_LO_REGS_H_ */
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