#ifndef ASIC_REG_DCORE0_MME_CTRL_LO_ARCH_BASE_ADDR_REGS_H_
#define ASIC_REG_DCORE0_MME_CTRL_LO_ARCH_BASE_ADDR_REGS_H_
#define mmDCORE0_MME_CTRL_LO_ARCH_BASE_ADDR_COUT1_LOW …
#define mmDCORE0_MME_CTRL_LO_ARCH_BASE_ADDR_COUT1_HIGH …
#define mmDCORE0_MME_CTRL_LO_ARCH_BASE_ADDR_COUT0_LOW …
#define mmDCORE0_MME_CTRL_LO_ARCH_BASE_ADDR_COUT0_HIGH …
#define mmDCORE0_MME_CTRL_LO_ARCH_BASE_ADDR_A_LOW …
#define mmDCORE0_MME_CTRL_LO_ARCH_BASE_ADDR_A_HIGH …
#define mmDCORE0_MME_CTRL_LO_ARCH_BASE_ADDR_B_LOW …
#define mmDCORE0_MME_CTRL_LO_ARCH_BASE_ADDR_B_HIGH …
#endif