linux/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_mme_ctrl_lo_arch_non_tensor_end_regs.h

/* SPDX-License-Identifier: GPL-2.0
 *
 * Copyright 2016-2020 HabanaLabs, Ltd.
 * All Rights Reserved.
 *
 */

/************************************
 ** This is an auto-generated file **
 **       DO NOT EDIT BELOW        **
 ************************************/

#ifndef ASIC_REG_DCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_REGS_H_
#define ASIC_REG_DCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_REGS_H_

/*
 *****************************************
 *   DCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END
 *   (Prototype: MME_NON_TENSOR_DESCRIPTOR)
 *****************************************
 */

#define mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_CONV_KERNEL_SIZE_MINUS_1 …

#define mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_CONV_LOW …

#define mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_CONV_HIGH …

#define mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_OUTER_LOOP …

#define mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_NUM_ITERATIONS_MINUS_1 …

#define mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_SB_REPEAT …

#define mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_FP8_BIAS …

#define mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_RATE_LIMITER …

#define mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_USER_DATA …

#define mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_PERF_EVT_IN …

#define mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_PERF_EVT_OUT …

#define mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_PCU …

#define mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_SLAVE_SYNC_OBJ0_ADDR …

#define mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_SLAVE_SYNC_OBJ1_ADDR …

#define mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_POWER_LOOP …

#define mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_SPARE0_MASTER …

#define mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_SPARE1_MASTER …

#define mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_SPARE2_MASTER …

#define mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_SPARE3_MASTER …

#define mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_SPARE0_SLAVE …

#define mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_SPARE1_SLAVE …

#define mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_SPARE2_SLAVE …

#define mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_SPARE3_SLAVE …

#define mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_WKL_ID …

#endif /* ASIC_REG_DCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_REGS_H_ */