/* SPDX-License-Identifier: GPL-2.0 * * Copyright 2016-2020 HabanaLabs, Ltd. * All Rights Reserved. * */ /************************************ ** This is an auto-generated file ** ** DO NOT EDIT BELOW ** ************************************/ #ifndef ASIC_REG_PDMA0_CORE_SPECIAL_MASKS_H_ #define ASIC_REG_PDMA0_CORE_SPECIAL_MASKS_H_ /* ***************************************** * PDMA0_CORE_SPECIAL * (Prototype: SPECIAL_REGS) ***************************************** */ /* PDMA0_CORE_SPECIAL_GLBL_PRIV */ #define PDMA0_CORE_SPECIAL_GLBL_PRIV_VAL_SHIFT … #define PDMA0_CORE_SPECIAL_GLBL_PRIV_VAL_MASK … /* PDMA0_CORE_SPECIAL_MEM_GW_DATA */ #define PDMA0_CORE_SPECIAL_MEM_GW_DATA_VAL_SHIFT … #define PDMA0_CORE_SPECIAL_MEM_GW_DATA_VAL_MASK … /* PDMA0_CORE_SPECIAL_MEM_GW_REQ */ #define PDMA0_CORE_SPECIAL_MEM_GW_REQ_ADDR_SHIFT … #define PDMA0_CORE_SPECIAL_MEM_GW_REQ_ADDR_MASK … #define PDMA0_CORE_SPECIAL_MEM_GW_REQ_MID_SHIFT … #define PDMA0_CORE_SPECIAL_MEM_GW_REQ_MID_MASK … #define PDMA0_CORE_SPECIAL_MEM_GW_REQ_WNR_SHIFT … #define PDMA0_CORE_SPECIAL_MEM_GW_REQ_WNR_MASK … #define PDMA0_CORE_SPECIAL_MEM_GW_REQ_VLD_SHIFT … #define PDMA0_CORE_SPECIAL_MEM_GW_REQ_VLD_MASK … /* PDMA0_CORE_SPECIAL_MEM_NUMOF */ #define PDMA0_CORE_SPECIAL_MEM_NUMOF_VAL_SHIFT … #define PDMA0_CORE_SPECIAL_MEM_NUMOF_VAL_MASK … /* PDMA0_CORE_SPECIAL_MEM_ECC_SEL */ #define PDMA0_CORE_SPECIAL_MEM_ECC_SEL_VAL_SHIFT … #define PDMA0_CORE_SPECIAL_MEM_ECC_SEL_VAL_MASK … /* PDMA0_CORE_SPECIAL_MEM_ECC_CTL */ #define PDMA0_CORE_SPECIAL_MEM_ECC_CTL_SERR_INJ_SHIFT … #define PDMA0_CORE_SPECIAL_MEM_ECC_CTL_SERR_INJ_MASK … #define PDMA0_CORE_SPECIAL_MEM_ECC_CTL_DERR_INJ_SHIFT … #define PDMA0_CORE_SPECIAL_MEM_ECC_CTL_DERR_INJ_MASK … #define PDMA0_CORE_SPECIAL_MEM_ECC_CTL_SERR_CLR_SHIFT … #define PDMA0_CORE_SPECIAL_MEM_ECC_CTL_SERR_CLR_MASK … #define PDMA0_CORE_SPECIAL_MEM_ECC_CTL_DERR_CLR_SHIFT … #define PDMA0_CORE_SPECIAL_MEM_ECC_CTL_DERR_CLR_MASK … /* PDMA0_CORE_SPECIAL_MEM_ECC_ERR_MASK */ #define PDMA0_CORE_SPECIAL_MEM_ECC_ERR_MASK_SERR_SHIFT … #define PDMA0_CORE_SPECIAL_MEM_ECC_ERR_MASK_SERR_MASK … #define PDMA0_CORE_SPECIAL_MEM_ECC_ERR_MASK_DERR_SHIFT … #define PDMA0_CORE_SPECIAL_MEM_ECC_ERR_MASK_DERR_MASK … /* PDMA0_CORE_SPECIAL_MEM_ECC_GLBL_ERR_MASK */ #define PDMA0_CORE_SPECIAL_MEM_ECC_GLBL_ERR_MASK_SERR_SHIFT … #define PDMA0_CORE_SPECIAL_MEM_ECC_GLBL_ERR_MASK_SERR_MASK … #define PDMA0_CORE_SPECIAL_MEM_ECC_GLBL_ERR_MASK_DERR_SHIFT … #define PDMA0_CORE_SPECIAL_MEM_ECC_GLBL_ERR_MASK_DERR_MASK … /* PDMA0_CORE_SPECIAL_MEM_ECC_ERR_STS */ #define PDMA0_CORE_SPECIAL_MEM_ECC_ERR_STS_SYND_SHIFT … #define PDMA0_CORE_SPECIAL_MEM_ECC_ERR_STS_SYND_MASK … #define PDMA0_CORE_SPECIAL_MEM_ECC_ERR_STS_SERR_SHIFT … #define PDMA0_CORE_SPECIAL_MEM_ECC_ERR_STS_SERR_MASK … #define PDMA0_CORE_SPECIAL_MEM_ECC_ERR_STS_DERR_SHIFT … #define PDMA0_CORE_SPECIAL_MEM_ECC_ERR_STS_DERR_MASK … /* PDMA0_CORE_SPECIAL_MEM_ECC_ERR_ADDR */ #define PDMA0_CORE_SPECIAL_MEM_ECC_ERR_ADDR_VAL_SHIFT … #define PDMA0_CORE_SPECIAL_MEM_ECC_ERR_ADDR_VAL_MASK … /* PDMA0_CORE_SPECIAL_MEM_RM */ #define PDMA0_CORE_SPECIAL_MEM_RM_VAL_SHIFT … #define PDMA0_CORE_SPECIAL_MEM_RM_VAL_MASK … /* PDMA0_CORE_SPECIAL_GLBL_ERR_MASK */ #define PDMA0_CORE_SPECIAL_GLBL_ERR_MASK_APB_PRIV_RD_SHIFT … #define PDMA0_CORE_SPECIAL_GLBL_ERR_MASK_APB_PRIV_RD_MASK … #define PDMA0_CORE_SPECIAL_GLBL_ERR_MASK_APB_SEC_RD_SHIFT … #define PDMA0_CORE_SPECIAL_GLBL_ERR_MASK_APB_SEC_RD_MASK … #define PDMA0_CORE_SPECIAL_GLBL_ERR_MASK_APB_UNMAPPED_RD_SHIFT … #define PDMA0_CORE_SPECIAL_GLBL_ERR_MASK_APB_UNMAPPED_RD_MASK … #define PDMA0_CORE_SPECIAL_GLBL_ERR_MASK_APB_PRIV_WR_SHIFT … #define PDMA0_CORE_SPECIAL_GLBL_ERR_MASK_APB_PRIV_WR_MASK … #define PDMA0_CORE_SPECIAL_GLBL_ERR_MASK_APB_SEC_WR_SHIFT … #define PDMA0_CORE_SPECIAL_GLBL_ERR_MASK_APB_SEC_WR_MASK … #define PDMA0_CORE_SPECIAL_GLBL_ERR_MASK_APB_UNMAPPED_WR_SHIFT … #define PDMA0_CORE_SPECIAL_GLBL_ERR_MASK_APB_UNMAPPED_WR_MASK … #define PDMA0_CORE_SPECIAL_GLBL_ERR_MASK_EXT_SEC_WR_SHIFT … #define PDMA0_CORE_SPECIAL_GLBL_ERR_MASK_EXT_SEC_WR_MASK … #define PDMA0_CORE_SPECIAL_GLBL_ERR_MASK_EXT_UNMAPPED_WR_SHIFT … #define PDMA0_CORE_SPECIAL_GLBL_ERR_MASK_EXT_UNMAPPED_WR_MASK … /* PDMA0_CORE_SPECIAL_GLBL_ERR_ADDR */ #define PDMA0_CORE_SPECIAL_GLBL_ERR_ADDR_VAL_SHIFT … #define PDMA0_CORE_SPECIAL_GLBL_ERR_ADDR_VAL_MASK … /* PDMA0_CORE_SPECIAL_GLBL_ERR_CAUSE */ #define PDMA0_CORE_SPECIAL_GLBL_ERR_CAUSE_APB_PRIV_RD_SHIFT … #define PDMA0_CORE_SPECIAL_GLBL_ERR_CAUSE_APB_PRIV_RD_MASK … #define PDMA0_CORE_SPECIAL_GLBL_ERR_CAUSE_APB_SEC_RD_SHIFT … #define PDMA0_CORE_SPECIAL_GLBL_ERR_CAUSE_APB_SEC_RD_MASK … #define PDMA0_CORE_SPECIAL_GLBL_ERR_CAUSE_APB_UNMAPPED_RD_SHIFT … #define PDMA0_CORE_SPECIAL_GLBL_ERR_CAUSE_APB_UNMAPPED_RD_MASK … #define PDMA0_CORE_SPECIAL_GLBL_ERR_CAUSE_APB_PRIV_WR_SHIFT … #define PDMA0_CORE_SPECIAL_GLBL_ERR_CAUSE_APB_PRIV_WR_MASK … #define PDMA0_CORE_SPECIAL_GLBL_ERR_CAUSE_APB_SEC_WR_SHIFT … #define PDMA0_CORE_SPECIAL_GLBL_ERR_CAUSE_APB_SEC_WR_MASK … #define PDMA0_CORE_SPECIAL_GLBL_ERR_CAUSE_APB_UNMAPPED_WR_SHIFT … #define PDMA0_CORE_SPECIAL_GLBL_ERR_CAUSE_APB_UNMAPPED_WR_MASK … #define PDMA0_CORE_SPECIAL_GLBL_ERR_CAUSE_EXT_SEC_WR_SHIFT … #define PDMA0_CORE_SPECIAL_GLBL_ERR_CAUSE_EXT_SEC_WR_MASK … #define PDMA0_CORE_SPECIAL_GLBL_ERR_CAUSE_EXT_UNMAPPED_WR_SHIFT … #define PDMA0_CORE_SPECIAL_GLBL_ERR_CAUSE_EXT_UNMAPPED_WR_MASK … /* PDMA0_CORE_SPECIAL_GLBL_SPARE */ #define PDMA0_CORE_SPECIAL_GLBL_SPARE_R_SHIFT … #define PDMA0_CORE_SPECIAL_GLBL_SPARE_R_MASK … /* PDMA0_CORE_SPECIAL_GLBL_SEC */ #define PDMA0_CORE_SPECIAL_GLBL_SEC_VAL_SHIFT … #define PDMA0_CORE_SPECIAL_GLBL_SEC_VAL_MASK … #endif /* ASIC_REG_PDMA0_CORE_SPECIAL_MASKS_H_ */
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