/* SPDX-License-Identifier: GPL-2.0 * * Copyright 2016-2020 HabanaLabs, Ltd. * All Rights Reserved. * */ /************************************ ** This is an auto-generated file ** ** DO NOT EDIT BELOW ** ************************************/ #ifndef ASIC_REG_DCORE0_SYNC_MNGR_GLBL_MASKS_H_ #define ASIC_REG_DCORE0_SYNC_MNGR_GLBL_MASKS_H_ /* ***************************************** * DCORE0_SYNC_MNGR_GLBL * (Prototype: SOB_GLBL) ***************************************** */ /* DCORE0_SYNC_MNGR_GLBL_SM_SEI_MASK */ #define DCORE0_SYNC_MNGR_GLBL_SM_SEI_MASK_SO_OVERFLOW_SHIFT … #define DCORE0_SYNC_MNGR_GLBL_SM_SEI_MASK_SO_OVERFLOW_MASK … #define DCORE0_SYNC_MNGR_GLBL_SM_SEI_MASK_MST_UNALIGN4B_SHIFT … #define DCORE0_SYNC_MNGR_GLBL_SM_SEI_MASK_MST_UNALIGN4B_MASK … #define DCORE0_SYNC_MNGR_GLBL_SM_SEI_MASK_MST_RSP_ERR_SHIFT … #define DCORE0_SYNC_MNGR_GLBL_SM_SEI_MASK_MST_RSP_ERR_MASK … /* DCORE0_SYNC_MNGR_GLBL_SM_SEI_CAUSE */ #define DCORE0_SYNC_MNGR_GLBL_SM_SEI_CAUSE_CAUSE_SHIFT … #define DCORE0_SYNC_MNGR_GLBL_SM_SEI_CAUSE_CAUSE_MASK … #define DCORE0_SYNC_MNGR_GLBL_SM_SEI_CAUSE_LOG_SHIFT … #define DCORE0_SYNC_MNGR_GLBL_SM_SEI_CAUSE_LOG_MASK … /* DCORE0_SYNC_MNGR_GLBL_L2H_CPMR_L */ #define DCORE0_SYNC_MNGR_GLBL_L2H_CPMR_L_VAL_SHIFT … #define DCORE0_SYNC_MNGR_GLBL_L2H_CPMR_L_VAL_MASK … /* DCORE0_SYNC_MNGR_GLBL_L2H_CPMR_H */ #define DCORE0_SYNC_MNGR_GLBL_L2H_CPMR_H_VAL_SHIFT … #define DCORE0_SYNC_MNGR_GLBL_L2H_CPMR_H_VAL_MASK … /* DCORE0_SYNC_MNGR_GLBL_L2H_MASK_L */ #define DCORE0_SYNC_MNGR_GLBL_L2H_MASK_L_VAL_SHIFT … #define DCORE0_SYNC_MNGR_GLBL_L2H_MASK_L_VAL_MASK … /* DCORE0_SYNC_MNGR_GLBL_L2H_MASK_H */ #define DCORE0_SYNC_MNGR_GLBL_L2H_MASK_H_VAL_SHIFT … #define DCORE0_SYNC_MNGR_GLBL_L2H_MASK_H_VAL_MASK … /* DCORE0_SYNC_MNGR_GLBL_ASID_SEC */ #define DCORE0_SYNC_MNGR_GLBL_ASID_SEC_ASID_SHIFT … #define DCORE0_SYNC_MNGR_GLBL_ASID_SEC_ASID_MASK … #define DCORE0_SYNC_MNGR_GLBL_ASID_SEC_BP_MMU_SHIFT … #define DCORE0_SYNC_MNGR_GLBL_ASID_SEC_BP_MMU_MASK … /* DCORE0_SYNC_MNGR_GLBL_ASID_PRIV_ONLY */ #define DCORE0_SYNC_MNGR_GLBL_ASID_PRIV_ONLY_ASID_SHIFT … #define DCORE0_SYNC_MNGR_GLBL_ASID_PRIV_ONLY_ASID_MASK … #define DCORE0_SYNC_MNGR_GLBL_ASID_PRIV_ONLY_BP_MMU_SHIFT … #define DCORE0_SYNC_MNGR_GLBL_ASID_PRIV_ONLY_BP_MMU_MASK … /* DCORE0_SYNC_MNGR_GLBL_LBW_DELAY */ #define DCORE0_SYNC_MNGR_GLBL_LBW_DELAY_VAL_SHIFT … #define DCORE0_SYNC_MNGR_GLBL_LBW_DELAY_VAL_MASK … #define DCORE0_SYNC_MNGR_GLBL_LBW_DELAY_EN_SHIFT … #define DCORE0_SYNC_MNGR_GLBL_LBW_DELAY_EN_MASK … /* DCORE0_SYNC_MNGR_GLBL_PI_SIZE */ #define DCORE0_SYNC_MNGR_GLBL_PI_SIZE_VAL_SHIFT … #define DCORE0_SYNC_MNGR_GLBL_PI_SIZE_VAL_MASK … /* DCORE0_SYNC_MNGR_GLBL_SOB_ONLY */ #define DCORE0_SYNC_MNGR_GLBL_SOB_ONLY_EN_SHIFT … #define DCORE0_SYNC_MNGR_GLBL_SOB_ONLY_EN_MASK … /* DCORE0_SYNC_MNGR_GLBL_CQ_INTR */ #define DCORE0_SYNC_MNGR_GLBL_CQ_INTR_CQ_SEC_INTR_SHIFT … #define DCORE0_SYNC_MNGR_GLBL_CQ_INTR_CQ_SEC_INTR_MASK … #define DCORE0_SYNC_MNGR_GLBL_CQ_INTR_CQ_SEC_INTR_MASK_SHIFT … #define DCORE0_SYNC_MNGR_GLBL_CQ_INTR_CQ_SEC_INTR_MASK_MASK … #define DCORE0_SYNC_MNGR_GLBL_CQ_INTR_CQ_INTR_QUEUE_INDEX_SHIFT … #define DCORE0_SYNC_MNGR_GLBL_CQ_INTR_CQ_INTR_QUEUE_INDEX_MASK … /* DCORE0_SYNC_MNGR_GLBL_ASID_NONE_SEC_PRIV */ #define DCORE0_SYNC_MNGR_GLBL_ASID_NONE_SEC_PRIV_ASID_SHIFT … #define DCORE0_SYNC_MNGR_GLBL_ASID_NONE_SEC_PRIV_ASID_MASK … #define DCORE0_SYNC_MNGR_GLBL_ASID_NONE_SEC_PRIV_BP_MMU_SHIFT … #define DCORE0_SYNC_MNGR_GLBL_ASID_NONE_SEC_PRIV_BP_MMU_MASK … /* DCORE0_SYNC_MNGR_GLBL_PI_INC_MODE_SIZE */ #define DCORE0_SYNC_MNGR_GLBL_PI_INC_MODE_SIZE_VAL_SHIFT … #define DCORE0_SYNC_MNGR_GLBL_PI_INC_MODE_SIZE_VAL_MASK … /* DCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L */ #define DCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_VAL_SHIFT … #define DCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_VAL_MASK … /* DCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H */ #define DCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_VAL_SHIFT … #define DCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_VAL_MASK … /* DCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2 */ #define DCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_VAL_SHIFT … #define DCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_VAL_MASK … /* DCORE0_SYNC_MNGR_GLBL_CQ_PI */ #define DCORE0_SYNC_MNGR_GLBL_CQ_PI_VAL_SHIFT … #define DCORE0_SYNC_MNGR_GLBL_CQ_PI_VAL_MASK … /* DCORE0_SYNC_MNGR_GLBL_CQ_SEC */ #define DCORE0_SYNC_MNGR_GLBL_CQ_SEC_SEC_SHIFT … #define DCORE0_SYNC_MNGR_GLBL_CQ_SEC_SEC_MASK … #define DCORE0_SYNC_MNGR_GLBL_CQ_SEC_PRIV_SHIFT … #define DCORE0_SYNC_MNGR_GLBL_CQ_SEC_PRIV_MASK … /* DCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L */ #define DCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_ADDRL_SHIFT … #define DCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_ADDRL_MASK … /* DCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H */ #define DCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_ADDRH_SHIFT … #define DCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_ADDRH_MASK … /* DCORE0_SYNC_MNGR_GLBL_LBW_DATA */ #define DCORE0_SYNC_MNGR_GLBL_LBW_DATA_VAL_SHIFT … #define DCORE0_SYNC_MNGR_GLBL_LBW_DATA_VAL_MASK … /* DCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE */ #define DCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_MODE_SHIFT … #define DCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_MODE_MASK … #endif /* ASIC_REG_DCORE0_SYNC_MNGR_GLBL_MASKS_H_ */
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