/* SPDX-License-Identifier: GPL-2.0 * * Copyright 2016-2020 HabanaLabs, Ltd. * All Rights Reserved. * */ /************************************ ** This is an auto-generated file ** ** DO NOT EDIT BELOW ** ************************************/ #ifndef ASIC_REG_DCORE0_TPC0_CFG_MASKS_H_ #define ASIC_REG_DCORE0_TPC0_CFG_MASKS_H_ /* ***************************************** * DCORE0_TPC0_CFG * (Prototype: TPC) ***************************************** */ /* DCORE0_TPC0_CFG_TPC_COUNT */ #define DCORE0_TPC0_CFG_TPC_COUNT_V_SHIFT … #define DCORE0_TPC0_CFG_TPC_COUNT_V_MASK … /* DCORE0_TPC0_CFG_TPC_ID */ #define DCORE0_TPC0_CFG_TPC_ID_V_SHIFT … #define DCORE0_TPC0_CFG_TPC_ID_V_MASK … /* DCORE0_TPC0_CFG_STALL_ON_ERR */ #define DCORE0_TPC0_CFG_STALL_ON_ERR_V_SHIFT … #define DCORE0_TPC0_CFG_STALL_ON_ERR_V_MASK … /* DCORE0_TPC0_CFG_CLK_EN */ #define DCORE0_TPC0_CFG_CLK_EN_LBW_CFG_DIS_SHIFT … #define DCORE0_TPC0_CFG_CLK_EN_LBW_CFG_DIS_MASK … #define DCORE0_TPC0_CFG_CLK_EN_DBG_CFG_DIS_SHIFT … #define DCORE0_TPC0_CFG_CLK_EN_DBG_CFG_DIS_MASK … /* DCORE0_TPC0_CFG_IQ_RL_EN */ #define DCORE0_TPC0_CFG_IQ_RL_EN_V_SHIFT … #define DCORE0_TPC0_CFG_IQ_RL_EN_V_MASK … /* DCORE0_TPC0_CFG_IQ_RL_SAT */ #define DCORE0_TPC0_CFG_IQ_RL_SAT_V_SHIFT … #define DCORE0_TPC0_CFG_IQ_RL_SAT_V_MASK … /* DCORE0_TPC0_CFG_IQ_RL_RST_TOKEN */ #define DCORE0_TPC0_CFG_IQ_RL_RST_TOKEN_V_SHIFT … #define DCORE0_TPC0_CFG_IQ_RL_RST_TOKEN_V_MASK … /* DCORE0_TPC0_CFG_IQ_RL_TIMEOUT */ #define DCORE0_TPC0_CFG_IQ_RL_TIMEOUT_V_SHIFT … #define DCORE0_TPC0_CFG_IQ_RL_TIMEOUT_V_MASK … /* DCORE0_TPC0_CFG_TSB_CFG_MTRR_2 */ #define DCORE0_TPC0_CFG_TSB_CFG_MTRR_2_PHY_BASE_ADD_LO_SHIFT … #define DCORE0_TPC0_CFG_TSB_CFG_MTRR_2_PHY_BASE_ADD_LO_MASK … /* DCORE0_TPC0_CFG_IQ_LBW_CLK_EN */ #define DCORE0_TPC0_CFG_IQ_LBW_CLK_EN_V_SHIFT … #define DCORE0_TPC0_CFG_IQ_LBW_CLK_EN_V_MASK … /* DCORE0_TPC0_CFG_TPC_LOCK_VALUE */ #define DCORE0_TPC0_CFG_TPC_LOCK_VALUE_VALUE_SHIFT … #define DCORE0_TPC0_CFG_TPC_LOCK_VALUE_VALUE_MASK … /* DCORE0_TPC0_CFG_TPC_LOCK */ #define DCORE0_TPC0_CFG_TPC_LOCK_LOCK_SHIFT … #define DCORE0_TPC0_CFG_TPC_LOCK_LOCK_MASK … /* DCORE0_TPC0_CFG_CGU_SB */ #define DCORE0_TPC0_CFG_CGU_SB_TSB_DISABLE_SHIFT … #define DCORE0_TPC0_CFG_CGU_SB_TSB_DISABLE_MASK … /* DCORE0_TPC0_CFG_CGU_CNT */ #define DCORE0_TPC0_CFG_CGU_CNT_DCACHE_DISABLE_SHIFT … #define DCORE0_TPC0_CFG_CGU_CNT_DCACHE_DISABLE_MASK … #define DCORE0_TPC0_CFG_CGU_CNT_WQ_DISABLE_SHIFT … #define DCORE0_TPC0_CFG_CGU_CNT_WQ_DISABLE_MASK … #define DCORE0_TPC0_CFG_CGU_CNT_SPU_AGU_ADDSUB_0_DISABLE_SHIFT … #define DCORE0_TPC0_CFG_CGU_CNT_SPU_AGU_ADDSUB_0_DISABLE_MASK … #define DCORE0_TPC0_CFG_CGU_CNT_SPU_AGU_ADDSUB_1_DISABLE_SHIFT … #define DCORE0_TPC0_CFG_CGU_CNT_SPU_AGU_ADDSUB_1_DISABLE_MASK … #define DCORE0_TPC0_CFG_CGU_CNT_SPU_AGU_ADDSUB_2_DISABLE_SHIFT … #define DCORE0_TPC0_CFG_CGU_CNT_SPU_AGU_ADDSUB_2_DISABLE_MASK … #define DCORE0_TPC0_CFG_CGU_CNT_SPU_AGU_ADDSUB_3_DISABLE_SHIFT … #define DCORE0_TPC0_CFG_CGU_CNT_SPU_AGU_ADDSUB_3_DISABLE_MASK … #define DCORE0_TPC0_CFG_CGU_CNT_SPU_AGU_ADDSUB_4_DISABLE_SHIFT … #define DCORE0_TPC0_CFG_CGU_CNT_SPU_AGU_ADDSUB_4_DISABLE_MASK … #define DCORE0_TPC0_CFG_CGU_CNT_SPU_AGU_CMP_0_DISABLE_SHIFT … #define DCORE0_TPC0_CFG_CGU_CNT_SPU_AGU_CMP_0_DISABLE_MASK … #define DCORE0_TPC0_CFG_CGU_CNT_SPU_AGU_CMP_1_DISABLE_SHIFT … #define DCORE0_TPC0_CFG_CGU_CNT_SPU_AGU_CMP_1_DISABLE_MASK … #define DCORE0_TPC0_CFG_CGU_CNT_SPU_AGU_CMP_2_DISABLE_SHIFT … #define DCORE0_TPC0_CFG_CGU_CNT_SPU_AGU_CMP_2_DISABLE_MASK … #define DCORE0_TPC0_CFG_CGU_CNT_SPU_AGU_CMP_3_DISABLE_SHIFT … #define DCORE0_TPC0_CFG_CGU_CNT_SPU_AGU_CMP_3_DISABLE_MASK … #define DCORE0_TPC0_CFG_CGU_CNT_SPU_AGU_CMP_4_DISABLE_SHIFT … #define DCORE0_TPC0_CFG_CGU_CNT_SPU_AGU_CMP_4_DISABLE_MASK … #define DCORE0_TPC0_CFG_CGU_CNT_MSAC_DISABLE_SHIFT … #define DCORE0_TPC0_CFG_CGU_CNT_MSAC_DISABLE_MASK … #define DCORE0_TPC0_CFG_CGU_CNT_CONV_DISABLE_SHIFT … #define DCORE0_TPC0_CFG_CGU_CNT_CONV_DISABLE_MASK … #define DCORE0_TPC0_CFG_CGU_CNT_NEARBYINT_DISABLE_SHIFT … #define DCORE0_TPC0_CFG_CGU_CNT_NEARBYINT_DISABLE_MASK … #define DCORE0_TPC0_CFG_CGU_CNT_CMP_DISABLE_SHIFT … #define DCORE0_TPC0_CFG_CGU_CNT_CMP_DISABLE_MASK … #define DCORE0_TPC0_CFG_CGU_CNT_FP_MAC_DISABLE_SHIFT … #define DCORE0_TPC0_CFG_CGU_CNT_FP_MAC_DISABLE_MASK … #define DCORE0_TPC0_CFG_CGU_CNT_SOPS_SRC_A_D2_DISABLE_SHIFT … #define DCORE0_TPC0_CFG_CGU_CNT_SOPS_SRC_A_D2_DISABLE_MASK … #define DCORE0_TPC0_CFG_CGU_CNT_SOPS_SRC_B_D2_DISABLE_SHIFT … #define DCORE0_TPC0_CFG_CGU_CNT_SOPS_SRC_B_D2_DISABLE_MASK … #define DCORE0_TPC0_CFG_CGU_CNT_SOPS_SRC_E_D2_DISABLE_SHIFT … #define DCORE0_TPC0_CFG_CGU_CNT_SOPS_SRC_E_D2_DISABLE_MASK … #define DCORE0_TPC0_CFG_CGU_CNT_SOPS_FMA_SRC_C_E1_DISABLE_SHIFT … #define DCORE0_TPC0_CFG_CGU_CNT_SOPS_FMA_SRC_C_E1_DISABLE_MASK … #define DCORE0_TPC0_CFG_CGU_CNT_LD_SOPS_SRC_A_D2_DISABLE_SHIFT … #define DCORE0_TPC0_CFG_CGU_CNT_LD_SOPS_SRC_A_D2_DISABLE_MASK … #define DCORE0_TPC0_CFG_CGU_CNT_ST_SOPS_SRC_A_D2_DISABLE_SHIFT … #define DCORE0_TPC0_CFG_CGU_CNT_ST_SOPS_SRC_A_D2_DISABLE_MASK … #define DCORE0_TPC0_CFG_CGU_CNT_FP_ADDSUB_DISABLE_SHIFT … #define DCORE0_TPC0_CFG_CGU_CNT_FP_ADDSUB_DISABLE_MASK … /* DCORE0_TPC0_CFG_CGU_CPE */ #define DCORE0_TPC0_CFG_CGU_CPE_NEARBYINT_DISABLE_SHIFT … #define DCORE0_TPC0_CFG_CGU_CPE_NEARBYINT_DISABLE_MASK … #define DCORE0_TPC0_CFG_CGU_CPE_SOPS_SRC_A_DISABLE_SHIFT … #define DCORE0_TPC0_CFG_CGU_CPE_SOPS_SRC_A_DISABLE_MASK … #define DCORE0_TPC0_CFG_CGU_CPE_SOPS_SRC_B_DISABLE_SHIFT … #define DCORE0_TPC0_CFG_CGU_CPE_SOPS_SRC_B_DISABLE_MASK … #define DCORE0_TPC0_CFG_CGU_CPE_SOPS_SRC_E_DISABLE_SHIFT … #define DCORE0_TPC0_CFG_CGU_CPE_SOPS_SRC_E_DISABLE_MASK … #define DCORE0_TPC0_CFG_CGU_CPE_SOPS_SRC_D_DISABLE_SHIFT … #define DCORE0_TPC0_CFG_CGU_CPE_SOPS_SRC_D_DISABLE_MASK … #define DCORE0_TPC0_CFG_CGU_CPE_SOPS_SRC_C_DISABLE_SHIFT … #define DCORE0_TPC0_CFG_CGU_CPE_SOPS_SRC_C_DISABLE_MASK … #define DCORE0_TPC0_CFG_CGU_CPE_LD_SOPS_SRC_A_DISABLE_SHIFT … #define DCORE0_TPC0_CFG_CGU_CPE_LD_SOPS_SRC_A_DISABLE_MASK … #define DCORE0_TPC0_CFG_CGU_CPE_MSAC_DISABLE_SHIFT … #define DCORE0_TPC0_CFG_CGU_CPE_MSAC_DISABLE_MASK … #define DCORE0_TPC0_CFG_CGU_CPE_ADDSUB_DISABLE_SHIFT … #define DCORE0_TPC0_CFG_CGU_CPE_ADDSUB_DISABLE_MASK … #define DCORE0_TPC0_CFG_CGU_CPE_SHIFT_DISABLE_SHIFT … #define DCORE0_TPC0_CFG_CGU_CPE_SHIFT_DISABLE_MASK … #define DCORE0_TPC0_CFG_CGU_CPE_GLE_DISABLE_SHIFT … #define DCORE0_TPC0_CFG_CGU_CPE_GLE_DISABLE_MASK … #define DCORE0_TPC0_CFG_CGU_CPE_CMP_DISABLE_SHIFT … #define DCORE0_TPC0_CFG_CGU_CPE_CMP_DISABLE_MASK … #define DCORE0_TPC0_CFG_CGU_CPE_CONV_DISABLE_SHIFT … #define DCORE0_TPC0_CFG_CGU_CPE_CONV_DISABLE_MASK … #define DCORE0_TPC0_CFG_CGU_CPE_SB_DISABLE_SHIFT … #define DCORE0_TPC0_CFG_CGU_CPE_SB_DISABLE_MASK … #define DCORE0_TPC0_CFG_CGU_CPE_TBUF_DISABLE_SHIFT … #define DCORE0_TPC0_CFG_CGU_CPE_TBUF_DISABLE_MASK … #define DCORE0_TPC0_CFG_CGU_CPE_ST_G_DISABLE_SHIFT … #define DCORE0_TPC0_CFG_CGU_CPE_ST_G_DISABLE_MASK … #define DCORE0_TPC0_CFG_CGU_CPE_FP_MAC_0_DISABLE_SHIFT … #define DCORE0_TPC0_CFG_CGU_CPE_FP_MAC_0_DISABLE_MASK … #define DCORE0_TPC0_CFG_CGU_CPE_FP_MAC_1_DISABLE_SHIFT … #define DCORE0_TPC0_CFG_CGU_CPE_FP_MAC_1_DISABLE_MASK … #define DCORE0_TPC0_CFG_CGU_CPE_FP_ADDSUB_DISABLE_SHIFT … #define DCORE0_TPC0_CFG_CGU_CPE_FP_ADDSUB_DISABLE_MASK … #define DCORE0_TPC0_CFG_CGU_CPE_ST_SOPS_SRC_C_DISABLE_SHIFT … #define DCORE0_TPC0_CFG_CGU_CPE_ST_SOPS_SRC_C_DISABLE_MASK … /* DCORE0_TPC0_CFG_FP16_FTZ_IN */ #define DCORE0_TPC0_CFG_FP16_FTZ_IN_MODE_SHIFT … #define DCORE0_TPC0_CFG_FP16_FTZ_IN_MODE_MASK … /* DCORE0_TPC0_CFG_DCACHE_CFG */ #define DCORE0_TPC0_CFG_DCACHE_CFG_G_PREF_DIS_SHIFT … #define DCORE0_TPC0_CFG_DCACHE_CFG_G_PREF_DIS_MASK … #define DCORE0_TPC0_CFG_DCACHE_CFG_G_PREF_VLD_CLR_SHIFT … #define DCORE0_TPC0_CFG_DCACHE_CFG_G_PREF_VLD_CLR_MASK … #define DCORE0_TPC0_CFG_DCACHE_CFG_HALT_FLUSH_SHIFT … #define DCORE0_TPC0_CFG_DCACHE_CFG_HALT_FLUSH_MASK … #define DCORE0_TPC0_CFG_DCACHE_CFG_DEALIGN_DIS_SHIFT … #define DCORE0_TPC0_CFG_DCACHE_CFG_DEALIGN_DIS_MASK … /* DCORE0_TPC0_CFG_E2E_CRDT_TOP */ #define DCORE0_TPC0_CFG_E2E_CRDT_TOP_FORCE_EN_SHIFT … #define DCORE0_TPC0_CFG_E2E_CRDT_TOP_FORCE_EN_MASK … #define DCORE0_TPC0_CFG_E2E_CRDT_TOP_Y_X_FORCE_SHIFT … #define DCORE0_TPC0_CFG_E2E_CRDT_TOP_Y_X_FORCE_MASK … /* DCORE0_TPC0_CFG_TPC_DCACHE_L0CD */ #define DCORE0_TPC0_CFG_TPC_DCACHE_L0CD_VAL_SHIFT … #define DCORE0_TPC0_CFG_TPC_DCACHE_L0CD_VAL_MASK … /* DCORE0_TPC0_CFG_TPC_SB_L0CD */ #define DCORE0_TPC0_CFG_TPC_SB_L0CD_VAL_SHIFT … #define DCORE0_TPC0_CFG_TPC_SB_L0CD_VAL_MASK … /* DCORE0_TPC0_CFG_CONV_ROUND_CSR */ #define DCORE0_TPC0_CFG_CONV_ROUND_CSR_MODE_SHIFT … #define DCORE0_TPC0_CFG_CONV_ROUND_CSR_MODE_MASK … /* DCORE0_TPC0_CFG_TSB_OCCUPANCY */ #define DCORE0_TPC0_CFG_TSB_OCCUPANCY_V_SHIFT … #define DCORE0_TPC0_CFG_TSB_OCCUPANCY_V_MASK … /* DCORE0_TPC0_CFG_ARB_QNT_HBW_WEIGHT */ #define DCORE0_TPC0_CFG_ARB_QNT_HBW_WEIGHT_AR_SHIFT … #define DCORE0_TPC0_CFG_ARB_QNT_HBW_WEIGHT_AR_MASK … #define DCORE0_TPC0_CFG_ARB_QNT_HBW_WEIGHT_AW_SHIFT … #define DCORE0_TPC0_CFG_ARB_QNT_HBW_WEIGHT_AW_MASK … /* DCORE0_TPC0_CFG_ARB_QNT_LBW_WEIGHT */ #define DCORE0_TPC0_CFG_ARB_QNT_LBW_WEIGHT_AW_SHIFT … #define DCORE0_TPC0_CFG_ARB_QNT_LBW_WEIGHT_AW_MASK … #define DCORE0_TPC0_CFG_ARB_QNT_LBW_WEIGHT_AR_SHIFT … #define DCORE0_TPC0_CFG_ARB_QNT_LBW_WEIGHT_AR_MASK … /* DCORE0_TPC0_CFG_ARB_CNT_HBW_WEIGHT */ #define DCORE0_TPC0_CFG_ARB_CNT_HBW_WEIGHT_AR_SHIFT … #define DCORE0_TPC0_CFG_ARB_CNT_HBW_WEIGHT_AR_MASK … #define DCORE0_TPC0_CFG_ARB_CNT_HBW_WEIGHT_AW_SHIFT … #define DCORE0_TPC0_CFG_ARB_CNT_HBW_WEIGHT_AW_MASK … /* DCORE0_TPC0_CFG_ARB_CNT_LBW_WEIGHT */ #define DCORE0_TPC0_CFG_ARB_CNT_LBW_WEIGHT_AR_SHIFT … #define DCORE0_TPC0_CFG_ARB_CNT_LBW_WEIGHT_AR_MASK … #define DCORE0_TPC0_CFG_ARB_CNT_LBW_WEIGHT_AW_SHIFT … #define DCORE0_TPC0_CFG_ARB_CNT_LBW_WEIGHT_AW_MASK … /* DCORE0_TPC0_CFG_LUT_FUNC32_BASE2_ADDR_LO */ #define DCORE0_TPC0_CFG_LUT_FUNC32_BASE2_ADDR_LO_V_SHIFT … #define DCORE0_TPC0_CFG_LUT_FUNC32_BASE2_ADDR_LO_V_MASK … /* DCORE0_TPC0_CFG_LUT_FUNC32_BASE2_ADDR_HI */ #define DCORE0_TPC0_CFG_LUT_FUNC32_BASE2_ADDR_HI_V_SHIFT … #define DCORE0_TPC0_CFG_LUT_FUNC32_BASE2_ADDR_HI_V_MASK … /* DCORE0_TPC0_CFG_LUT_FUNC64_BASE2_ADDR_LO */ #define DCORE0_TPC0_CFG_LUT_FUNC64_BASE2_ADDR_LO_V_SHIFT … #define DCORE0_TPC0_CFG_LUT_FUNC64_BASE2_ADDR_LO_V_MASK … /* DCORE0_TPC0_CFG_LUT_FUNC64_BASE2_ADDR_HI */ #define DCORE0_TPC0_CFG_LUT_FUNC64_BASE2_ADDR_HI_V_SHIFT … #define DCORE0_TPC0_CFG_LUT_FUNC64_BASE2_ADDR_HI_V_MASK … /* DCORE0_TPC0_CFG_LUT_FUNC128_BASE2_ADDR_LO */ #define DCORE0_TPC0_CFG_LUT_FUNC128_BASE2_ADDR_LO_V_SHIFT … #define DCORE0_TPC0_CFG_LUT_FUNC128_BASE2_ADDR_LO_V_MASK … /* DCORE0_TPC0_CFG_LUT_FUNC128_BASE2_ADDR_HI */ #define DCORE0_TPC0_CFG_LUT_FUNC128_BASE2_ADDR_HI_V_SHIFT … #define DCORE0_TPC0_CFG_LUT_FUNC128_BASE2_ADDR_HI_V_MASK … /* DCORE0_TPC0_CFG_LUT_FUNC256_BASE2_ADDR_LO */ #define DCORE0_TPC0_CFG_LUT_FUNC256_BASE2_ADDR_LO_V_SHIFT … #define DCORE0_TPC0_CFG_LUT_FUNC256_BASE2_ADDR_LO_V_MASK … /* DCORE0_TPC0_CFG_LUT_FUNC256_BASE2_ADDR_HI */ #define DCORE0_TPC0_CFG_LUT_FUNC256_BASE2_ADDR_HI_V_SHIFT … #define DCORE0_TPC0_CFG_LUT_FUNC256_BASE2_ADDR_HI_V_MASK … /* DCORE0_TPC0_CFG_SPE_LFSR_POLYNOM */ #define DCORE0_TPC0_CFG_SPE_LFSR_POLYNOM_V_SHIFT … #define DCORE0_TPC0_CFG_SPE_LFSR_POLYNOM_V_MASK … /* DCORE0_TPC0_CFG_TSB_CFG_MTRR_GLBL */ #define DCORE0_TPC0_CFG_TSB_CFG_MTRR_GLBL_EN_SHIFT … #define DCORE0_TPC0_CFG_TSB_CFG_MTRR_GLBL_EN_MASK … #define DCORE0_TPC0_CFG_TSB_CFG_MTRR_GLBL_DEFAULT_MEMORY_TYPE_SHIFT … #define DCORE0_TPC0_CFG_TSB_CFG_MTRR_GLBL_DEFAULT_MEMORY_TYPE_MASK … /* DCORE0_TPC0_CFG_TSB_CFG_MTRR */ #define DCORE0_TPC0_CFG_TSB_CFG_MTRR_VALID_SHIFT … #define DCORE0_TPC0_CFG_TSB_CFG_MTRR_VALID_MASK … #define DCORE0_TPC0_CFG_TSB_CFG_MTRR_MEMORY_TYPE_SHIFT … #define DCORE0_TPC0_CFG_TSB_CFG_MTRR_MEMORY_TYPE_MASK … #define DCORE0_TPC0_CFG_TSB_CFG_MTRR_PHY_BASE_ADD_SHIFT … #define DCORE0_TPC0_CFG_TSB_CFG_MTRR_PHY_BASE_ADD_MASK … /* DCORE0_TPC0_CFG_TSB_CFG_MTRR_MASK_LO */ #define DCORE0_TPC0_CFG_TSB_CFG_MTRR_MASK_LO_V_SHIFT … #define DCORE0_TPC0_CFG_TSB_CFG_MTRR_MASK_LO_V_MASK … /* DCORE0_TPC0_CFG_TSB_CFG_MTRR_MASK_HI */ #define DCORE0_TPC0_CFG_TSB_CFG_MTRR_MASK_HI_V_SHIFT … #define DCORE0_TPC0_CFG_TSB_CFG_MTRR_MASK_HI_V_MASK … /* DCORE0_TPC0_CFG_FP8_143_BIAS */ #define DCORE0_TPC0_CFG_FP8_143_BIAS_BIAS_143_SHIFT … #define DCORE0_TPC0_CFG_FP8_143_BIAS_BIAS_143_MASK … /* DCORE0_TPC0_CFG_ROUND_CSR */ #define DCORE0_TPC0_CFG_ROUND_CSR_MODE_SHIFT … #define DCORE0_TPC0_CFG_ROUND_CSR_MODE_MASK … /* DCORE0_TPC0_CFG_HB_PROT */ #define DCORE0_TPC0_CFG_HB_PROT_AWPROT_SHIFT … #define DCORE0_TPC0_CFG_HB_PROT_AWPROT_MASK … #define DCORE0_TPC0_CFG_HB_PROT_ARPROT_SHIFT … #define DCORE0_TPC0_CFG_HB_PROT_ARPROT_MASK … /* DCORE0_TPC0_CFG_LB_PROT */ #define DCORE0_TPC0_CFG_LB_PROT_AWPROT_SHIFT … #define DCORE0_TPC0_CFG_LB_PROT_AWPROT_MASK … #define DCORE0_TPC0_CFG_LB_PROT_ARPROT_SHIFT … #define DCORE0_TPC0_CFG_LB_PROT_ARPROT_MASK … /* DCORE0_TPC0_CFG_SEMAPHORE */ #define DCORE0_TPC0_CFG_SEMAPHORE_V_SHIFT … #define DCORE0_TPC0_CFG_SEMAPHORE_V_MASK … /* DCORE0_TPC0_CFG_VFLAGS */ #define DCORE0_TPC0_CFG_VFLAGS_V_SHIFT … #define DCORE0_TPC0_CFG_VFLAGS_V_MASK … /* DCORE0_TPC0_CFG_SFLAGS */ #define DCORE0_TPC0_CFG_SFLAGS_V_SHIFT … #define DCORE0_TPC0_CFG_SFLAGS_V_MASK … /* DCORE0_TPC0_CFG_LFSR_POLYNOM */ #define DCORE0_TPC0_CFG_LFSR_POLYNOM_V_SHIFT … #define DCORE0_TPC0_CFG_LFSR_POLYNOM_V_MASK … /* DCORE0_TPC0_CFG_STATUS */ #define DCORE0_TPC0_CFG_STATUS_SCALAR_PIPE_EMPTY_SHIFT … #define DCORE0_TPC0_CFG_STATUS_SCALAR_PIPE_EMPTY_MASK … #define DCORE0_TPC0_CFG_STATUS_VECTOR_PIPE_EMPTY_SHIFT … #define DCORE0_TPC0_CFG_STATUS_VECTOR_PIPE_EMPTY_MASK … #define DCORE0_TPC0_CFG_STATUS_IQ_EMPTY_SHIFT … #define DCORE0_TPC0_CFG_STATUS_IQ_EMPTY_MASK … #define DCORE0_TPC0_CFG_STATUS_SB_EMPTY_SHIFT … #define DCORE0_TPC0_CFG_STATUS_SB_EMPTY_MASK … #define DCORE0_TPC0_CFG_STATUS_QM_IDLE_SHIFT … #define DCORE0_TPC0_CFG_STATUS_QM_IDLE_MASK … #define DCORE0_TPC0_CFG_STATUS_QM_RDY_SHIFT … #define DCORE0_TPC0_CFG_STATUS_QM_RDY_MASK … /* DCORE0_TPC0_CFG_CFG_BASE_ADDRESS_HIGH */ #define DCORE0_TPC0_CFG_CFG_BASE_ADDRESS_HIGH_V_SHIFT … #define DCORE0_TPC0_CFG_CFG_BASE_ADDRESS_HIGH_V_MASK … /* DCORE0_TPC0_CFG_CFG_SUBTRACT_VALUE */ #define DCORE0_TPC0_CFG_CFG_SUBTRACT_VALUE_V_SHIFT … #define DCORE0_TPC0_CFG_CFG_SUBTRACT_VALUE_V_MASK … /* DCORE0_TPC0_CFG_SM_BASE_ADDRESS_HIGH */ #define DCORE0_TPC0_CFG_SM_BASE_ADDRESS_HIGH_V_SHIFT … #define DCORE0_TPC0_CFG_SM_BASE_ADDRESS_HIGH_V_MASK … /* DCORE0_TPC0_CFG_TPC_CMD */ #define DCORE0_TPC0_CFG_TPC_CMD_ICACHE_INVALIDATE_SHIFT … #define DCORE0_TPC0_CFG_TPC_CMD_ICACHE_INVALIDATE_MASK … #define DCORE0_TPC0_CFG_TPC_CMD_DCACHE_INVALIDATE_SHIFT … #define DCORE0_TPC0_CFG_TPC_CMD_DCACHE_INVALIDATE_MASK … #define DCORE0_TPC0_CFG_TPC_CMD_LCACHE_INVALIDATE_SHIFT … #define DCORE0_TPC0_CFG_TPC_CMD_LCACHE_INVALIDATE_MASK … #define DCORE0_TPC0_CFG_TPC_CMD_TCACHE_INVALIDATE_SHIFT … #define DCORE0_TPC0_CFG_TPC_CMD_TCACHE_INVALIDATE_MASK … #define DCORE0_TPC0_CFG_TPC_CMD_ICACHE_PREFETCH_64KB_SHIFT … #define DCORE0_TPC0_CFG_TPC_CMD_ICACHE_PREFETCH_64KB_MASK … #define DCORE0_TPC0_CFG_TPC_CMD_ICACHE_PREFETCH_32KB_SHIFT … #define DCORE0_TPC0_CFG_TPC_CMD_ICACHE_PREFETCH_32KB_MASK … #define DCORE0_TPC0_CFG_TPC_CMD_QMAN_STOP_SHIFT … #define DCORE0_TPC0_CFG_TPC_CMD_QMAN_STOP_MASK … /* DCORE0_TPC0_CFG_TPC_EXECUTE */ #define DCORE0_TPC0_CFG_TPC_EXECUTE_V_SHIFT … #define DCORE0_TPC0_CFG_TPC_EXECUTE_V_MASK … /* DCORE0_TPC0_CFG_TPC_STALL */ #define DCORE0_TPC0_CFG_TPC_STALL_V_SHIFT … #define DCORE0_TPC0_CFG_TPC_STALL_V_MASK … /* DCORE0_TPC0_CFG_ICACHE_BASE_ADDERESS_LOW */ #define DCORE0_TPC0_CFG_ICACHE_BASE_ADDERESS_LOW_V_SHIFT … #define DCORE0_TPC0_CFG_ICACHE_BASE_ADDERESS_LOW_V_MASK … /* DCORE0_TPC0_CFG_ICACHE_BASE_ADDERESS_HIGH */ #define DCORE0_TPC0_CFG_ICACHE_BASE_ADDERESS_HIGH_V_SHIFT … #define DCORE0_TPC0_CFG_ICACHE_BASE_ADDERESS_HIGH_V_MASK … /* DCORE0_TPC0_CFG_RD_RATE_LIMIT */ #define DCORE0_TPC0_CFG_RD_RATE_LIMIT_ENABLE_SHIFT … #define DCORE0_TPC0_CFG_RD_RATE_LIMIT_ENABLE_MASK … #define DCORE0_TPC0_CFG_RD_RATE_LIMIT_SATURATION_SHIFT … #define DCORE0_TPC0_CFG_RD_RATE_LIMIT_SATURATION_MASK … #define DCORE0_TPC0_CFG_RD_RATE_LIMIT_TIMEOUT_SHIFT … #define DCORE0_TPC0_CFG_RD_RATE_LIMIT_TIMEOUT_MASK … /* DCORE0_TPC0_CFG_WR_RATE_LIMIT */ #define DCORE0_TPC0_CFG_WR_RATE_LIMIT_ENABLE_SHIFT … #define DCORE0_TPC0_CFG_WR_RATE_LIMIT_ENABLE_MASK … #define DCORE0_TPC0_CFG_WR_RATE_LIMIT_SATURATION_SHIFT … #define DCORE0_TPC0_CFG_WR_RATE_LIMIT_SATURATION_MASK … #define DCORE0_TPC0_CFG_WR_RATE_LIMIT_TIMEOUT_SHIFT … #define DCORE0_TPC0_CFG_WR_RATE_LIMIT_TIMEOUT_MASK … /* DCORE0_TPC0_CFG_MSS_CONFIG */ #define DCORE0_TPC0_CFG_MSS_CONFIG_AWCACHE_SHIFT … #define DCORE0_TPC0_CFG_MSS_CONFIG_AWCACHE_MASK … #define DCORE0_TPC0_CFG_MSS_CONFIG_ARCACHE_SHIFT … #define DCORE0_TPC0_CFG_MSS_CONFIG_ARCACHE_MASK … #define DCORE0_TPC0_CFG_MSS_CONFIG_ICACHE_FETCH_LINE_NUM_SHIFT … #define DCORE0_TPC0_CFG_MSS_CONFIG_ICACHE_FETCH_LINE_NUM_MASK … #define DCORE0_TPC0_CFG_MSS_CONFIG_EXPOSED_PIPE_DIS_SHIFT … #define DCORE0_TPC0_CFG_MSS_CONFIG_EXPOSED_PIPE_DIS_MASK … #define DCORE0_TPC0_CFG_MSS_CONFIG_DCACHE_PREFETCH_DIS_SHIFT … #define DCORE0_TPC0_CFG_MSS_CONFIG_DCACHE_PREFETCH_DIS_MASK … /* DCORE0_TPC0_CFG_TPC_INTR_CAUSE */ #define DCORE0_TPC0_CFG_TPC_INTR_CAUSE_CAUSE_SHIFT … #define DCORE0_TPC0_CFG_TPC_INTR_CAUSE_CAUSE_MASK … /* DCORE0_TPC0_CFG_TPC_INTR_MASK */ #define DCORE0_TPC0_CFG_TPC_INTR_MASK_MASK_SHIFT … #define DCORE0_TPC0_CFG_TPC_INTR_MASK_MASK_MASK … /* DCORE0_TPC0_CFG_WQ_CREDITS */ #define DCORE0_TPC0_CFG_WQ_CREDITS_ST_G_SHIFT … #define DCORE0_TPC0_CFG_WQ_CREDITS_ST_G_MASK … #define DCORE0_TPC0_CFG_WQ_CREDITS_KERNEL_FIFO_SHIFT … #define DCORE0_TPC0_CFG_WQ_CREDITS_KERNEL_FIFO_MASK … /* DCORE0_TPC0_CFG_OPCODE_EXEC */ #define DCORE0_TPC0_CFG_OPCODE_EXEC_SPU_OP_SHIFT … #define DCORE0_TPC0_CFG_OPCODE_EXEC_SPU_OP_MASK … #define DCORE0_TPC0_CFG_OPCODE_EXEC_SPU_EN_SHIFT … #define DCORE0_TPC0_CFG_OPCODE_EXEC_SPU_EN_MASK … #define DCORE0_TPC0_CFG_OPCODE_EXEC_VPU_OP_SHIFT … #define DCORE0_TPC0_CFG_OPCODE_EXEC_VPU_OP_MASK … #define DCORE0_TPC0_CFG_OPCODE_EXEC_VPU_EN_SHIFT … #define DCORE0_TPC0_CFG_OPCODE_EXEC_VPU_EN_MASK … #define DCORE0_TPC0_CFG_OPCODE_EXEC_LD_OP_SHIFT … #define DCORE0_TPC0_CFG_OPCODE_EXEC_LD_OP_MASK … #define DCORE0_TPC0_CFG_OPCODE_EXEC_LD_EN_SHIFT … #define DCORE0_TPC0_CFG_OPCODE_EXEC_LD_EN_MASK … #define DCORE0_TPC0_CFG_OPCODE_EXEC_ST_OP_SHIFT … #define DCORE0_TPC0_CFG_OPCODE_EXEC_ST_OP_MASK … #define DCORE0_TPC0_CFG_OPCODE_EXEC_ST_EN_SHIFT … #define DCORE0_TPC0_CFG_OPCODE_EXEC_ST_EN_MASK … /* DCORE0_TPC0_CFG_LUT_FUNC32_BASE_ADDR_LO */ #define DCORE0_TPC0_CFG_LUT_FUNC32_BASE_ADDR_LO_V_SHIFT … #define DCORE0_TPC0_CFG_LUT_FUNC32_BASE_ADDR_LO_V_MASK … /* DCORE0_TPC0_CFG_LUT_FUNC32_BASE_ADDR_HI */ #define DCORE0_TPC0_CFG_LUT_FUNC32_BASE_ADDR_HI_V_SHIFT … #define DCORE0_TPC0_CFG_LUT_FUNC32_BASE_ADDR_HI_V_MASK … /* DCORE0_TPC0_CFG_LUT_FUNC64_BASE_ADDR_LO */ #define DCORE0_TPC0_CFG_LUT_FUNC64_BASE_ADDR_LO_V_SHIFT … #define DCORE0_TPC0_CFG_LUT_FUNC64_BASE_ADDR_LO_V_MASK … /* DCORE0_TPC0_CFG_LUT_FUNC64_BASE_ADDR_HI */ #define DCORE0_TPC0_CFG_LUT_FUNC64_BASE_ADDR_HI_V_SHIFT … #define DCORE0_TPC0_CFG_LUT_FUNC64_BASE_ADDR_HI_V_MASK … /* DCORE0_TPC0_CFG_LUT_FUNC128_BASE_ADDR_LO */ #define DCORE0_TPC0_CFG_LUT_FUNC128_BASE_ADDR_LO_V_SHIFT … #define DCORE0_TPC0_CFG_LUT_FUNC128_BASE_ADDR_LO_V_MASK … /* DCORE0_TPC0_CFG_LUT_FUNC128_BASE_ADDR_HI */ #define DCORE0_TPC0_CFG_LUT_FUNC128_BASE_ADDR_HI_V_SHIFT … #define DCORE0_TPC0_CFG_LUT_FUNC128_BASE_ADDR_HI_V_MASK … /* DCORE0_TPC0_CFG_LUT_FUNC256_BASE_ADDR_LO */ #define DCORE0_TPC0_CFG_LUT_FUNC256_BASE_ADDR_LO_V_SHIFT … #define DCORE0_TPC0_CFG_LUT_FUNC256_BASE_ADDR_LO_V_MASK … /* DCORE0_TPC0_CFG_LUT_FUNC256_BASE_ADDR_HI */ #define DCORE0_TPC0_CFG_LUT_FUNC256_BASE_ADDR_HI_V_SHIFT … #define DCORE0_TPC0_CFG_LUT_FUNC256_BASE_ADDR_HI_V_MASK … /* DCORE0_TPC0_CFG_TSB_CFG_MAX_SIZE */ #define DCORE0_TPC0_CFG_TSB_CFG_MAX_SIZE_DATA_SHIFT … #define DCORE0_TPC0_CFG_TSB_CFG_MAX_SIZE_DATA_MASK … #define DCORE0_TPC0_CFG_TSB_CFG_MAX_SIZE_MD_SHIFT … #define DCORE0_TPC0_CFG_TSB_CFG_MAX_SIZE_MD_MASK … /* DCORE0_TPC0_CFG_TSB_CFG */ #define DCORE0_TPC0_CFG_TSB_CFG_CACHE_DISABLE_SHIFT … #define DCORE0_TPC0_CFG_TSB_CFG_CACHE_DISABLE_MASK … #define DCORE0_TPC0_CFG_TSB_CFG_MAX_OS_SHIFT … #define DCORE0_TPC0_CFG_TSB_CFG_MAX_OS_MASK … #define DCORE0_TPC0_CFG_TSB_CFG_ENABLE_CGATE_SHIFT … #define DCORE0_TPC0_CFG_TSB_CFG_ENABLE_CGATE_MASK … /* DCORE0_TPC0_CFG_TSB_INFLIGHT_CNTR */ #define DCORE0_TPC0_CFG_TSB_INFLIGHT_CNTR_V_SHIFT … #define DCORE0_TPC0_CFG_TSB_INFLIGHT_CNTR_V_MASK … /* DCORE0_TPC0_CFG_WQ_INFLIGHT_CNTR */ #define DCORE0_TPC0_CFG_WQ_INFLIGHT_CNTR_HBW_SHIFT … #define DCORE0_TPC0_CFG_WQ_INFLIGHT_CNTR_HBW_MASK … #define DCORE0_TPC0_CFG_WQ_INFLIGHT_CNTR_LBW_SHIFT … #define DCORE0_TPC0_CFG_WQ_INFLIGHT_CNTR_LBW_MASK … /* DCORE0_TPC0_CFG_WQ_LBW_TOTAL_CNTR */ #define DCORE0_TPC0_CFG_WQ_LBW_TOTAL_CNTR_V_SHIFT … #define DCORE0_TPC0_CFG_WQ_LBW_TOTAL_CNTR_V_MASK … /* DCORE0_TPC0_CFG_WQ_HBW_TOTAL_CNTR */ #define DCORE0_TPC0_CFG_WQ_HBW_TOTAL_CNTR_V_SHIFT … #define DCORE0_TPC0_CFG_WQ_HBW_TOTAL_CNTR_V_MASK … /* DCORE0_TPC0_CFG_IRQ_OCCOUPY_CNTR */ #define DCORE0_TPC0_CFG_IRQ_OCCOUPY_CNTR_V_SHIFT … #define DCORE0_TPC0_CFG_IRQ_OCCOUPY_CNTR_V_MASK … #endif /* ASIC_REG_DCORE0_TPC0_CFG_MASKS_H_ */
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