/* SPDX-License-Identifier: GPL-2.0 * * Copyright 2016-2020 HabanaLabs, Ltd. * All Rights Reserved. * */ /************************************ ** This is an auto-generated file ** ** DO NOT EDIT BELOW ** ************************************/ #ifndef ASIC_REG_DCORE0_MME_CTRL_LO_MASKS_H_ #define ASIC_REG_DCORE0_MME_CTRL_LO_MASKS_H_ /* ***************************************** * DCORE0_MME_CTRL_LO * (Prototype: MME_CTRL_LO) ***************************************** */ /* DCORE0_MME_CTRL_LO_ARCH_STATUS */ #define DCORE0_MME_CTRL_LO_ARCH_STATUS_AGU_IN_SHIFT … #define DCORE0_MME_CTRL_LO_ARCH_STATUS_AGU_IN_MASK … #define DCORE0_MME_CTRL_LO_ARCH_STATUS_EU_SHIFT … #define DCORE0_MME_CTRL_LO_ARCH_STATUS_EU_MASK … #define DCORE0_MME_CTRL_LO_ARCH_STATUS_AP_SHIFT … #define DCORE0_MME_CTRL_LO_ARCH_STATUS_AP_MASK … #define DCORE0_MME_CTRL_LO_ARCH_STATUS_AGU_COUT_SHIFT … #define DCORE0_MME_CTRL_LO_ARCH_STATUS_AGU_COUT_MASK … #define DCORE0_MME_CTRL_LO_ARCH_STATUS_SB_IN_EMPTY_SHIFT … #define DCORE0_MME_CTRL_LO_ARCH_STATUS_SB_IN_EMPTY_MASK … #define DCORE0_MME_CTRL_LO_ARCH_STATUS_AGU_COUT_SM_IDLE_SHIFT … #define DCORE0_MME_CTRL_LO_ARCH_STATUS_AGU_COUT_SM_IDLE_MASK … #define DCORE0_MME_CTRL_LO_ARCH_STATUS_WBC_AXI_IDLE_SHIFT … #define DCORE0_MME_CTRL_LO_ARCH_STATUS_WBC_AXI_IDLE_MASK … #define DCORE0_MME_CTRL_LO_ARCH_STATUS_SB_IN_AXI_IDLE_SHIFT … #define DCORE0_MME_CTRL_LO_ARCH_STATUS_SB_IN_AXI_IDLE_MASK … #define DCORE0_MME_CTRL_LO_ARCH_STATUS_ACCUM_FREE_SHIFT … #define DCORE0_MME_CTRL_LO_ARCH_STATUS_ACCUM_FREE_MASK … #define DCORE0_MME_CTRL_LO_ARCH_STATUS_QM_IDLE_SHIFT … #define DCORE0_MME_CTRL_LO_ARCH_STATUS_QM_IDLE_MASK … #define DCORE0_MME_CTRL_LO_ARCH_STATUS_QM_RDY_SHIFT … #define DCORE0_MME_CTRL_LO_ARCH_STATUS_QM_RDY_MASK … /* DCORE0_MME_CTRL_LO_CMD */ #define DCORE0_MME_CTRL_LO_CMD_AGU_IN_SHIFT … #define DCORE0_MME_CTRL_LO_CMD_AGU_IN_MASK … #define DCORE0_MME_CTRL_LO_CMD_EU_SHIFT … #define DCORE0_MME_CTRL_LO_CMD_EU_MASK … #define DCORE0_MME_CTRL_LO_CMD_AP_SHIFT … #define DCORE0_MME_CTRL_LO_CMD_AP_MASK … #define DCORE0_MME_CTRL_LO_CMD_AGU_COUT_SHIFT … #define DCORE0_MME_CTRL_LO_CMD_AGU_COUT_MASK … #define DCORE0_MME_CTRL_LO_CMD_COPY_AND_INC_SHIFT … #define DCORE0_MME_CTRL_LO_CMD_COPY_AND_INC_MASK … #define DCORE0_MME_CTRL_LO_CMD_DESC_SEL_SHIFT … #define DCORE0_MME_CTRL_LO_CMD_DESC_SEL_MASK … #define DCORE0_MME_CTRL_LO_CMD_MASK_IDLE_IND_SHIFT … #define DCORE0_MME_CTRL_LO_CMD_MASK_IDLE_IND_MASK … #define DCORE0_MME_CTRL_LO_CMD_AGU_OUT1_FROM_AGU0_DW0_SHIFT … #define DCORE0_MME_CTRL_LO_CMD_AGU_OUT1_FROM_AGU0_DW0_MASK … #define DCORE0_MME_CTRL_LO_CMD_AGU_OUT1_FROM_AGU0_DW1_4_SHIFT … #define DCORE0_MME_CTRL_LO_CMD_AGU_OUT1_FROM_AGU0_DW1_4_MASK … #define DCORE0_MME_CTRL_LO_CMD_NULL_DESC_SHIFT … #define DCORE0_MME_CTRL_LO_CMD_NULL_DESC_MASK … /* DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_DW0 */ #define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_DW0_SIGNAL_MASK0_SHIFT … #define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_DW0_SIGNAL_MASK0_MASK … #define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_DW0_SIGNAL_EN0_SHIFT … #define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_DW0_SIGNAL_EN0_MASK … #define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_DW0_SIGNAL_MASK1_SHIFT … #define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_DW0_SIGNAL_MASK1_MASK … #define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_DW0_SIGNAL_EN1_SHIFT … #define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_DW0_SIGNAL_EN1_MASK … #define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_DW0_MASTER_WAIT_SLAVE_FENCE_SHIFT … #define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_DW0_MASTER_WAIT_SLAVE_FENCE_MASK … #define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_DW0_SLAVE_SEND_FENCE2MASTER_SHIFT … #define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_DW0_SLAVE_SEND_FENCE2MASTER_MASK … #define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_DW0_SLAVE_SIGNAL_EN_SHIFT … #define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_DW0_SLAVE_SIGNAL_EN_MASK … #define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_DW0_SLAVE0_USE_SLV_ADR_SHIFT … #define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_DW0_SLAVE0_USE_SLV_ADR_MASK … #define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_DW0_SLAVE1_USE_SLV_ADR_SHIFT … #define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_DW0_SLAVE1_USE_SLV_ADR_MASK … #define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_DW0_SLAVE0_USE_MSTR_ADR_PLUS4_SHIFT … #define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_DW0_SLAVE0_USE_MSTR_ADR_PLUS4_MASK … #define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_DW0_SLAVE1_USE_MSTR_ADR_PLUS4_SHIFT … #define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_DW0_SLAVE1_USE_MSTR_ADR_PLUS4_MASK … /* DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_ADDR0 */ #define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_ADDR0_V_SHIFT … #define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_ADDR0_V_MASK … /* DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_VAL0 */ #define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_VAL0_SO_VALUE_SHIFT … #define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_VAL0_SO_VALUE_MASK … #define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_VAL0_SO_RESERVED_SHIFT … #define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_VAL0_SO_RESERVED_MASK … #define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_VAL0_SO_PERF_EN_SHIFT … #define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_VAL0_SO_PERF_EN_MASK … #define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_VAL0_SO_OP_SHIFT … #define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_VAL0_SO_OP_MASK … /* DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_ADDR1 */ #define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_ADDR1_V_SHIFT … #define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_ADDR1_V_MASK … /* DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_VAL1 */ #define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_VAL1_SO_VALUE_SHIFT … #define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_VAL1_SO_VALUE_MASK … #define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_VAL1_SO_RESERVED_SHIFT … #define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_VAL1_SO_RESERVED_MASK … #define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_VAL1_SO_PERF_EN_SHIFT … #define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_VAL1_SO_PERF_EN_MASK … #define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_VAL1_SO_OP_SHIFT … #define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_VAL1_SO_OP_MASK … /* DCORE0_MME_CTRL_LO_ARCH_A_SS */ #define DCORE0_MME_CTRL_LO_ARCH_A_SS_MINUS_1_SHIFT … #define DCORE0_MME_CTRL_LO_ARCH_A_SS_MINUS_1_MASK … /* DCORE0_MME_CTRL_LO_ARCH_B_SS */ #define DCORE0_MME_CTRL_LO_ARCH_B_SS_MINUS_1_SHIFT … #define DCORE0_MME_CTRL_LO_ARCH_B_SS_MINUS_1_MASK … /* DCORE0_MME_CTRL_LO_ARCH_COUT_SS */ #define DCORE0_MME_CTRL_LO_ARCH_COUT_SS_MINUS_1_SHIFT … #define DCORE0_MME_CTRL_LO_ARCH_COUT_SS_MINUS_1_MASK … /* DCORE0_MME_CTRL_LO_QM_STALL */ #define DCORE0_MME_CTRL_LO_QM_STALL_V_SHIFT … #define DCORE0_MME_CTRL_LO_QM_STALL_V_MASK … /* DCORE0_MME_CTRL_LO_LOG_SHADOW_LO */ #define DCORE0_MME_CTRL_LO_LOG_SHADOW_LO_MASK_0_SHIFT … #define DCORE0_MME_CTRL_LO_LOG_SHADOW_LO_MASK_0_MASK … #define DCORE0_MME_CTRL_LO_LOG_SHADOW_LO_MASK_1_SHIFT … #define DCORE0_MME_CTRL_LO_LOG_SHADOW_LO_MASK_1_MASK … /* DCORE0_MME_CTRL_LO_LOG_SHADOW_HI */ #define DCORE0_MME_CTRL_LO_LOG_SHADOW_HI_MASK_2_SHIFT … #define DCORE0_MME_CTRL_LO_LOG_SHADOW_HI_MASK_2_MASK … #define DCORE0_MME_CTRL_LO_LOG_SHADOW_HI_MASK_3_SHIFT … #define DCORE0_MME_CTRL_LO_LOG_SHADOW_HI_MASK_3_MASK … /* DCORE0_MME_CTRL_LO_SYNC_OBJECT_FIFO_TH */ #define DCORE0_MME_CTRL_LO_SYNC_OBJECT_FIFO_TH_V_SHIFT … #define DCORE0_MME_CTRL_LO_SYNC_OBJECT_FIFO_TH_V_MASK … /* DCORE0_MME_CTRL_LO_REDUN */ #define DCORE0_MME_CTRL_LO_REDUN_FMA_SHIFT … #define DCORE0_MME_CTRL_LO_REDUN_FMA_MASK … /* DCORE0_MME_CTRL_LO_EUS_LOCAL_FIFO_TH */ #define DCORE0_MME_CTRL_LO_EUS_LOCAL_FIFO_TH_FIFO0_SHIFT … #define DCORE0_MME_CTRL_LO_EUS_LOCAL_FIFO_TH_FIFO0_MASK … #define DCORE0_MME_CTRL_LO_EUS_LOCAL_FIFO_TH_FIFO1_SHIFT … #define DCORE0_MME_CTRL_LO_EUS_LOCAL_FIFO_TH_FIFO1_MASK … #define DCORE0_MME_CTRL_LO_EUS_LOCAL_FIFO_TH_FIFO2_SHIFT … #define DCORE0_MME_CTRL_LO_EUS_LOCAL_FIFO_TH_FIFO2_MASK … /* DCORE0_MME_CTRL_LO_EUS_ROLLUP_DLY_DW0 */ #define DCORE0_MME_CTRL_LO_EUS_ROLLUP_DLY_DW0_FP_SHIFT … #define DCORE0_MME_CTRL_LO_EUS_ROLLUP_DLY_DW0_FP_MASK … #define DCORE0_MME_CTRL_LO_EUS_ROLLUP_DLY_DW0_FP_PE0_SHIFT … #define DCORE0_MME_CTRL_LO_EUS_ROLLUP_DLY_DW0_FP_PE0_MASK … #define DCORE0_MME_CTRL_LO_EUS_ROLLUP_DLY_DW0_FP_PE1_SHIFT … #define DCORE0_MME_CTRL_LO_EUS_ROLLUP_DLY_DW0_FP_PE1_MASK … #define DCORE0_MME_CTRL_LO_EUS_ROLLUP_DLY_DW0_FP_PE2_SHIFT … #define DCORE0_MME_CTRL_LO_EUS_ROLLUP_DLY_DW0_FP_PE2_MASK … #define DCORE0_MME_CTRL_LO_EUS_ROLLUP_DLY_DW0_FP_PE3_SHIFT … #define DCORE0_MME_CTRL_LO_EUS_ROLLUP_DLY_DW0_FP_PE3_MASK … /* DCORE0_MME_CTRL_LO_EUS_ROLLUP_DLY_DW1 */ #define DCORE0_MME_CTRL_LO_EUS_ROLLUP_DLY_DW1_FP_PE4_SHIFT … #define DCORE0_MME_CTRL_LO_EUS_ROLLUP_DLY_DW1_FP_PE4_MASK … #define DCORE0_MME_CTRL_LO_EUS_ROLLUP_DLY_DW1_FP_PE_HI_SHIFT … #define DCORE0_MME_CTRL_LO_EUS_ROLLUP_DLY_DW1_FP_PE_HI_MASK … /* DCORE0_MME_CTRL_LO_EUS_ROLLUP_CD_PROT_F16 */ #define DCORE0_MME_CTRL_LO_EUS_ROLLUP_CD_PROT_F16_DLY_SHIFT … #define DCORE0_MME_CTRL_LO_EUS_ROLLUP_CD_PROT_F16_DLY_MASK … #define DCORE0_MME_CTRL_LO_EUS_ROLLUP_CD_PROT_F16_EN_SHIFT … #define DCORE0_MME_CTRL_LO_EUS_ROLLUP_CD_PROT_F16_EN_MASK … /* DCORE0_MME_CTRL_LO_EUS_ROLLUP_CD_PROT_F8 */ #define DCORE0_MME_CTRL_LO_EUS_ROLLUP_CD_PROT_F8_DLY_SHIFT … #define DCORE0_MME_CTRL_LO_EUS_ROLLUP_CD_PROT_F8_DLY_MASK … #define DCORE0_MME_CTRL_LO_EUS_ROLLUP_CD_PROT_F8_EN_SHIFT … #define DCORE0_MME_CTRL_LO_EUS_ROLLUP_CD_PROT_F8_EN_MASK … /* DCORE0_MME_CTRL_LO_EUS_ROLLUP_CD_PROT_FP32 */ #define DCORE0_MME_CTRL_LO_EUS_ROLLUP_CD_PROT_FP32_DLY_SHIFT … #define DCORE0_MME_CTRL_LO_EUS_ROLLUP_CD_PROT_FP32_DLY_MASK … #define DCORE0_MME_CTRL_LO_EUS_ROLLUP_CD_PROT_FP32_EN_SHIFT … #define DCORE0_MME_CTRL_LO_EUS_ROLLUP_CD_PROT_FP32_EN_MASK … /* DCORE0_MME_CTRL_LO_EUS_ROLLUP_CD_PROT_FP32I */ #define DCORE0_MME_CTRL_LO_EUS_ROLLUP_CD_PROT_FP32I_DLY_SHIFT … #define DCORE0_MME_CTRL_LO_EUS_ROLLUP_CD_PROT_FP32I_DLY_MASK … #define DCORE0_MME_CTRL_LO_EUS_ROLLUP_CD_PROT_FP32I_EN_SHIFT … #define DCORE0_MME_CTRL_LO_EUS_ROLLUP_CD_PROT_FP32I_EN_MASK … /* DCORE0_MME_CTRL_LO_EUS_ROLLUP_CD_PROT_TF32 */ #define DCORE0_MME_CTRL_LO_EUS_ROLLUP_CD_PROT_TF32_DLY_SHIFT … #define DCORE0_MME_CTRL_LO_EUS_ROLLUP_CD_PROT_TF32_DLY_MASK … #define DCORE0_MME_CTRL_LO_EUS_ROLLUP_CD_PROT_TF32_EN_SHIFT … #define DCORE0_MME_CTRL_LO_EUS_ROLLUP_CD_PROT_TF32_EN_MASK … /* DCORE0_MME_CTRL_LO_PCU_RL_DESC0 */ #define DCORE0_MME_CTRL_LO_PCU_RL_DESC0_RL_RST_TOKEN_SHIFT … #define DCORE0_MME_CTRL_LO_PCU_RL_DESC0_RL_RST_TOKEN_MASK … #define DCORE0_MME_CTRL_LO_PCU_RL_DESC0_RL_TIMEOUT_SHIFT … #define DCORE0_MME_CTRL_LO_PCU_RL_DESC0_RL_TIMEOUT_MASK … #define DCORE0_MME_CTRL_LO_PCU_RL_DESC0_RL_DUMMY2REAL_PERIOD_SHIFT … #define DCORE0_MME_CTRL_LO_PCU_RL_DESC0_RL_DUMMY2REAL_PERIOD_MASK … /* DCORE0_MME_CTRL_LO_PCU_RL_TOKEN_UPDATE */ #define DCORE0_MME_CTRL_LO_PCU_RL_TOKEN_UPDATE_INC_VAL_SHIFT … #define DCORE0_MME_CTRL_LO_PCU_RL_TOKEN_UPDATE_INC_VAL_MASK … #define DCORE0_MME_CTRL_LO_PCU_RL_TOKEN_UPDATE_DEC_VAL_SHIFT … #define DCORE0_MME_CTRL_LO_PCU_RL_TOKEN_UPDATE_DEC_VAL_MASK … /* DCORE0_MME_CTRL_LO_PCU_RL_TH */ #define DCORE0_MME_CTRL_LO_PCU_RL_TH_POOL_TH_DEC_SHIFT … #define DCORE0_MME_CTRL_LO_PCU_RL_TH_POOL_TH_DEC_MASK … #define DCORE0_MME_CTRL_LO_PCU_RL_TH_DUMMY_REAL_DIFF_TH_SHIFT … #define DCORE0_MME_CTRL_LO_PCU_RL_TH_DUMMY_REAL_DIFF_TH_MASK … /* DCORE0_MME_CTRL_LO_PCU_RL_MIN */ #define DCORE0_MME_CTRL_LO_PCU_RL_MIN_AVG_MIN_TO_FORCE_DUMMY_SHIFT … #define DCORE0_MME_CTRL_LO_PCU_RL_MIN_AVG_MIN_TO_FORCE_DUMMY_MASK … #define DCORE0_MME_CTRL_LO_PCU_RL_MIN_TOKEN_MIN_VAL_SHIFT … #define DCORE0_MME_CTRL_LO_PCU_RL_MIN_TOKEN_MIN_VAL_MASK … /* DCORE0_MME_CTRL_LO_PCU_RL_CTRL_EN */ #define DCORE0_MME_CTRL_LO_PCU_RL_CTRL_EN_PCU_DISABLE_SHIFT … #define DCORE0_MME_CTRL_LO_PCU_RL_CTRL_EN_PCU_DISABLE_MASK … #define DCORE0_MME_CTRL_LO_PCU_RL_CTRL_EN_MIN_VAL_PROT_EN_SHIFT … #define DCORE0_MME_CTRL_LO_PCU_RL_CTRL_EN_MIN_VAL_PROT_EN_MASK … /* DCORE0_MME_CTRL_LO_PCU_RL_HISTORY_LOG_SIZE */ #define DCORE0_MME_CTRL_LO_PCU_RL_HISTORY_LOG_SIZE_ALL_MACS_SHIFT … #define DCORE0_MME_CTRL_LO_PCU_RL_HISTORY_LOG_SIZE_ALL_MACS_MASK … #define DCORE0_MME_CTRL_LO_PCU_RL_HISTORY_LOG_SIZE_REAL_MACS_SHIFT … #define DCORE0_MME_CTRL_LO_PCU_RL_HISTORY_LOG_SIZE_REAL_MACS_MASK … /* DCORE0_MME_CTRL_LO_PCU_DUMMY_A_BF16 */ #define DCORE0_MME_CTRL_LO_PCU_DUMMY_A_BF16_ODD_SHIFT … #define DCORE0_MME_CTRL_LO_PCU_DUMMY_A_BF16_ODD_MASK … #define DCORE0_MME_CTRL_LO_PCU_DUMMY_A_BF16_EVEN_SHIFT … #define DCORE0_MME_CTRL_LO_PCU_DUMMY_A_BF16_EVEN_MASK … /* DCORE0_MME_CTRL_LO_PCU_DUMMY_B_BF16 */ #define DCORE0_MME_CTRL_LO_PCU_DUMMY_B_BF16_ODD_SHIFT … #define DCORE0_MME_CTRL_LO_PCU_DUMMY_B_BF16_ODD_MASK … #define DCORE0_MME_CTRL_LO_PCU_DUMMY_B_BF16_EVEN_SHIFT … #define DCORE0_MME_CTRL_LO_PCU_DUMMY_B_BF16_EVEN_MASK … /* DCORE0_MME_CTRL_LO_PCU_DUMMY_A_FP16 */ #define DCORE0_MME_CTRL_LO_PCU_DUMMY_A_FP16_ODD_SHIFT … #define DCORE0_MME_CTRL_LO_PCU_DUMMY_A_FP16_ODD_MASK … #define DCORE0_MME_CTRL_LO_PCU_DUMMY_A_FP16_EVEN_SHIFT … #define DCORE0_MME_CTRL_LO_PCU_DUMMY_A_FP16_EVEN_MASK … /* DCORE0_MME_CTRL_LO_PCU_DUMMY_B_FP16 */ #define DCORE0_MME_CTRL_LO_PCU_DUMMY_B_FP16_ODD_SHIFT … #define DCORE0_MME_CTRL_LO_PCU_DUMMY_B_FP16_ODD_MASK … #define DCORE0_MME_CTRL_LO_PCU_DUMMY_B_FP16_EVEN_SHIFT … #define DCORE0_MME_CTRL_LO_PCU_DUMMY_B_FP16_EVEN_MASK … /* DCORE0_MME_CTRL_LO_PCU_DUMMY_F8 */ #define DCORE0_MME_CTRL_LO_PCU_DUMMY_F8_A_VAL_ODD_SHIFT … #define DCORE0_MME_CTRL_LO_PCU_DUMMY_F8_A_VAL_ODD_MASK … #define DCORE0_MME_CTRL_LO_PCU_DUMMY_F8_A_VAL_EVEN_SHIFT … #define DCORE0_MME_CTRL_LO_PCU_DUMMY_F8_A_VAL_EVEN_MASK … #define DCORE0_MME_CTRL_LO_PCU_DUMMY_F8_B_VAL_ODD_SHIFT … #define DCORE0_MME_CTRL_LO_PCU_DUMMY_F8_B_VAL_ODD_MASK … #define DCORE0_MME_CTRL_LO_PCU_DUMMY_F8_B_VAL_EVEN_SHIFT … #define DCORE0_MME_CTRL_LO_PCU_DUMMY_F8_B_VAL_EVEN_MASK … /* DCORE0_MME_CTRL_LO_PCU_DUMMY_A_FP32_ODD */ #define DCORE0_MME_CTRL_LO_PCU_DUMMY_A_FP32_ODD_V_SHIFT … #define DCORE0_MME_CTRL_LO_PCU_DUMMY_A_FP32_ODD_V_MASK … /* DCORE0_MME_CTRL_LO_PCU_DUMMY_A_FP32_EVEN */ #define DCORE0_MME_CTRL_LO_PCU_DUMMY_A_FP32_EVEN_V_SHIFT … #define DCORE0_MME_CTRL_LO_PCU_DUMMY_A_FP32_EVEN_V_MASK … /* DCORE0_MME_CTRL_LO_PCU_DUMMY_B_FP32_ODD */ #define DCORE0_MME_CTRL_LO_PCU_DUMMY_B_FP32_ODD_V_SHIFT … #define DCORE0_MME_CTRL_LO_PCU_DUMMY_B_FP32_ODD_V_MASK … /* DCORE0_MME_CTRL_LO_PCU_DUMMY_B_FP32_EVEN */ #define DCORE0_MME_CTRL_LO_PCU_DUMMY_B_FP32_EVEN_V_SHIFT … #define DCORE0_MME_CTRL_LO_PCU_DUMMY_B_FP32_EVEN_V_MASK … /* DCORE0_MME_CTRL_LO_PCU_DUMMY_A_TF32_ODD */ #define DCORE0_MME_CTRL_LO_PCU_DUMMY_A_TF32_ODD_V_SHIFT … #define DCORE0_MME_CTRL_LO_PCU_DUMMY_A_TF32_ODD_V_MASK … /* DCORE0_MME_CTRL_LO_PCU_DUMMY_A_TF32_EVEN */ #define DCORE0_MME_CTRL_LO_PCU_DUMMY_A_TF32_EVEN_V_SHIFT … #define DCORE0_MME_CTRL_LO_PCU_DUMMY_A_TF32_EVEN_V_MASK … /* DCORE0_MME_CTRL_LO_PCU_DUMMY_B_TF32_ODD */ #define DCORE0_MME_CTRL_LO_PCU_DUMMY_B_TF32_ODD_V_SHIFT … #define DCORE0_MME_CTRL_LO_PCU_DUMMY_B_TF32_ODD_V_MASK … /* DCORE0_MME_CTRL_LO_PCU_DUMMY_B_TF32_EVEN */ #define DCORE0_MME_CTRL_LO_PCU_DUMMY_B_TF32_EVEN_V_SHIFT … #define DCORE0_MME_CTRL_LO_PCU_DUMMY_B_TF32_EVEN_V_MASK … /* DCORE0_MME_CTRL_LO_PROT */ #define DCORE0_MME_CTRL_LO_PROT_VALUE_SHIFT … #define DCORE0_MME_CTRL_LO_PROT_VALUE_MASK … /* DCORE0_MME_CTRL_LO_EU */ #define DCORE0_MME_CTRL_LO_EU_POWER_SAVE_DISABLE_SHIFT … #define DCORE0_MME_CTRL_LO_EU_POWER_SAVE_DISABLE_MASK … #define DCORE0_MME_CTRL_LO_EU_FP_PYR_CLOSE_CGATE_EN_SHIFT … #define DCORE0_MME_CTRL_LO_EU_FP_PYR_CLOSE_CGATE_EN_MASK … #define DCORE0_MME_CTRL_LO_EU_FP_CLS_CLOSE_CGATE_EN_SHIFT … #define DCORE0_MME_CTRL_LO_EU_FP_CLS_CLOSE_CGATE_EN_MASK … #define DCORE0_MME_CTRL_LO_EU_FP_CLOSE_CGATE_DLY_SHIFT … #define DCORE0_MME_CTRL_LO_EU_FP_CLOSE_CGATE_DLY_MASK … #define DCORE0_MME_CTRL_LO_EU_FP_CLOSE_CGATE_ON_DESC_SHIFT … #define DCORE0_MME_CTRL_LO_EU_FP_CLOSE_CGATE_ON_DESC_MASK … #define DCORE0_MME_CTRL_LO_EU_FP_ROLLUP_CDC_STALL_DIS_SHIFT … #define DCORE0_MME_CTRL_LO_EU_FP_ROLLUP_CDC_STALL_DIS_MASK … /* DCORE0_MME_CTRL_LO_SBTE */ #define DCORE0_MME_CTRL_LO_SBTE_CLOSE_CGATE_SHIFT … #define DCORE0_MME_CTRL_LO_SBTE_CLOSE_CGATE_MASK … /* DCORE0_MME_CTRL_LO_AGU_SM_INFLIGHT_CNTR */ #define DCORE0_MME_CTRL_LO_AGU_SM_INFLIGHT_CNTR_V_SHIFT … #define DCORE0_MME_CTRL_LO_AGU_SM_INFLIGHT_CNTR_V_MASK … /* DCORE0_MME_CTRL_LO_AGU_SM_TOTAL_CNTR */ #define DCORE0_MME_CTRL_LO_AGU_SM_TOTAL_CNTR_V_SHIFT … #define DCORE0_MME_CTRL_LO_AGU_SM_TOTAL_CNTR_V_MASK … /* DCORE0_MME_CTRL_LO_PCU_RL_SAT_SEC */ #define DCORE0_MME_CTRL_LO_PCU_RL_SAT_SEC_VAL_SHIFT … #define DCORE0_MME_CTRL_LO_PCU_RL_SAT_SEC_VAL_MASK … #define DCORE0_MME_CTRL_LO_PCU_RL_SAT_SEC_SEL_SHIFT … #define DCORE0_MME_CTRL_LO_PCU_RL_SAT_SEC_SEL_MASK … /* DCORE0_MME_CTRL_LO_FMA_FUNC_REDUN_CLK_EN32 */ #define DCORE0_MME_CTRL_LO_FMA_FUNC_REDUN_CLK_EN32_V_NMB__SHIFT … #define DCORE0_MME_CTRL_LO_FMA_FUNC_REDUN_CLK_EN32_V_NMB__MASK … /* DCORE0_MME_CTRL_LO_FMA_FUNC_REDUN_CLK_EN33 */ #define DCORE0_MME_CTRL_LO_FMA_FUNC_REDUN_CLK_EN33_V_NMB__SHIFT … #define DCORE0_MME_CTRL_LO_FMA_FUNC_REDUN_CLK_EN33_V_NMB__MASK … /* DCORE0_MME_CTRL_LO_EU_ISOLATION_DIS */ #define DCORE0_MME_CTRL_LO_EU_ISOLATION_DIS_FMA_SHIFT … #define DCORE0_MME_CTRL_LO_EU_ISOLATION_DIS_FMA_MASK … /* DCORE0_MME_CTRL_LO_QM_SLV_CLK_EN */ #define DCORE0_MME_CTRL_LO_QM_SLV_CLK_EN_V_SHIFT … #define DCORE0_MME_CTRL_LO_QM_SLV_CLK_EN_V_MASK … /* DCORE0_MME_CTRL_LO_HBW_CLK_ENABLER_DIS */ #define DCORE0_MME_CTRL_LO_HBW_CLK_ENABLER_DIS_AXI_SHIFT … #define DCORE0_MME_CTRL_LO_HBW_CLK_ENABLER_DIS_AXI_MASK … #define DCORE0_MME_CTRL_LO_HBW_CLK_ENABLER_DIS_APB_SHIFT … #define DCORE0_MME_CTRL_LO_HBW_CLK_ENABLER_DIS_APB_MASK … /* DCORE0_MME_CTRL_LO_AGU */ #define DCORE0_MME_CTRL_LO_AGU_COUT_H_FROM_SPATIAL_LOOP_SHIFT … #define DCORE0_MME_CTRL_LO_AGU_COUT_H_FROM_SPATIAL_LOOP_MASK … /* DCORE0_MME_CTRL_LO_QM */ #define DCORE0_MME_CTRL_LO_QM_STOP_ON_SBTE_ERR_SHIFT … #define DCORE0_MME_CTRL_LO_QM_STOP_ON_SBTE_ERR_MASK … #define DCORE0_MME_CTRL_LO_QM_EXT_ADDR_ERR_EN_SHIFT … #define DCORE0_MME_CTRL_LO_QM_EXT_ADDR_ERR_EN_MASK … /* DCORE0_MME_CTRL_LO_EARLY_RELEASE_STATUS */ #define DCORE0_MME_CTRL_LO_EARLY_RELEASE_STATUS_AGU_COUT0_SHIFT … #define DCORE0_MME_CTRL_LO_EARLY_RELEASE_STATUS_AGU_COUT0_MASK … #define DCORE0_MME_CTRL_LO_EARLY_RELEASE_STATUS_AGU_COUT1_SHIFT … #define DCORE0_MME_CTRL_LO_EARLY_RELEASE_STATUS_AGU_COUT1_MASK … #define DCORE0_MME_CTRL_LO_EARLY_RELEASE_STATUS_AP_BRAIN_SHIFT … #define DCORE0_MME_CTRL_LO_EARLY_RELEASE_STATUS_AP_BRAIN_MASK … #define DCORE0_MME_CTRL_LO_EARLY_RELEASE_STATUS_EU_BRAIN_SHIFT … #define DCORE0_MME_CTRL_LO_EARLY_RELEASE_STATUS_EU_BRAIN_MASK … /* DCORE0_MME_CTRL_LO_INTR_CAUSE */ #define DCORE0_MME_CTRL_LO_INTR_CAUSE_V_SHIFT … #define DCORE0_MME_CTRL_LO_INTR_CAUSE_V_MASK … /* DCORE0_MME_CTRL_LO_INTR_MASK */ #define DCORE0_MME_CTRL_LO_INTR_MASK_V_SHIFT … #define DCORE0_MME_CTRL_LO_INTR_MASK_V_MASK … /* DCORE0_MME_CTRL_LO_INTR_CLEAR */ #define DCORE0_MME_CTRL_LO_INTR_CLEAR_V_SHIFT … #define DCORE0_MME_CTRL_LO_INTR_CLEAR_V_MASK … /* DCORE0_MME_CTRL_LO_REDUN_PSOC_SEL_SEC */ #define DCORE0_MME_CTRL_LO_REDUN_PSOC_SEL_SEC_V_SHIFT … #define DCORE0_MME_CTRL_LO_REDUN_PSOC_SEL_SEC_V_MASK … /* DCORE0_MME_CTRL_LO_BIST */ #define DCORE0_MME_CTRL_LO_BIST_FUNC_MODE_SHIFT … #define DCORE0_MME_CTRL_LO_BIST_FUNC_MODE_MASK … #define DCORE0_MME_CTRL_LO_BIST_APB_SW_MODE_SHIFT … #define DCORE0_MME_CTRL_LO_BIST_APB_SW_MODE_MASK … /* DCORE0_MME_CTRL_LO_EU_RL_ENABLE */ #define DCORE0_MME_CTRL_LO_EU_RL_ENABLE_V_SHIFT … #define DCORE0_MME_CTRL_LO_EU_RL_ENABLE_V_MASK … /* DCORE0_MME_CTRL_LO_EU_RL_TOKEN_SEL */ #define DCORE0_MME_CTRL_LO_EU_RL_TOKEN_SEL_STAT_SHIFT … #define DCORE0_MME_CTRL_LO_EU_RL_TOKEN_SEL_STAT_MASK … /* DCORE0_MME_CTRL_LO_EU_RL_CFG */ #define DCORE0_MME_CTRL_LO_EU_RL_CFG_RST_TOKEN_SHIFT … #define DCORE0_MME_CTRL_LO_EU_RL_CFG_RST_TOKEN_MASK … #define DCORE0_MME_CTRL_LO_EU_RL_CFG_TIMEOUT_SHIFT … #define DCORE0_MME_CTRL_LO_EU_RL_CFG_TIMEOUT_MASK … #define DCORE0_MME_CTRL_LO_EU_RL_CFG_SATURATION_SHIFT … #define DCORE0_MME_CTRL_LO_EU_RL_CFG_SATURATION_MASK … #define DCORE0_MME_CTRL_LO_EU_RL_CFG_DATA_SIZE_SHIFT … #define DCORE0_MME_CTRL_LO_EU_RL_CFG_DATA_SIZE_MASK … /* DCORE0_MME_CTRL_LO_PCU_DBG_DW0 */ #define DCORE0_MME_CTRL_LO_PCU_DBG_DW0_FSM_STATE_SHIFT … #define DCORE0_MME_CTRL_LO_PCU_DBG_DW0_FSM_STATE_MASK … #define DCORE0_MME_CTRL_LO_PCU_DBG_DW0_REAL_POOL_TOKENS_SHIFT … #define DCORE0_MME_CTRL_LO_PCU_DBG_DW0_REAL_POOL_TOKENS_MASK … /* DCORE0_MME_CTRL_LO_PCU_DBG_DW1 */ #define DCORE0_MME_CTRL_LO_PCU_DBG_DW1_ALL_POOL_TOKENS_SHIFT … #define DCORE0_MME_CTRL_LO_PCU_DBG_DW1_ALL_POOL_TOKENS_MASK … /* DCORE0_MME_CTRL_LO_PCU_DBG_DW2 */ #define DCORE0_MME_CTRL_LO_PCU_DBG_DW2_BUBBLE_CYC_CNTR_SHIFT … #define DCORE0_MME_CTRL_LO_PCU_DBG_DW2_BUBBLE_CYC_CNTR_MASK … #define DCORE0_MME_CTRL_LO_PCU_DBG_DW2_DUMMY_CYC_CNTR_SHIFT … #define DCORE0_MME_CTRL_LO_PCU_DBG_DW2_DUMMY_CYC_CNTR_MASK … /* DCORE0_MME_CTRL_LO_PCU_DBG_DW3 */ #define DCORE0_MME_CTRL_LO_PCU_DBG_DW3_REAL_MACS_HISTORY_SHIFT … #define DCORE0_MME_CTRL_LO_PCU_DBG_DW3_REAL_MACS_HISTORY_MASK … #define DCORE0_MME_CTRL_LO_PCU_DBG_DW3_ALL_MACS_HISTORY_SHIFT … #define DCORE0_MME_CTRL_LO_PCU_DBG_DW3_ALL_MACS_HISTORY_MASK … /* DCORE0_MME_CTRL_LO_PCU_DBG_WKL_ID */ #define DCORE0_MME_CTRL_LO_PCU_DBG_WKL_ID_B_SHIFT … #define DCORE0_MME_CTRL_LO_PCU_DBG_WKL_ID_B_MASK … /* DCORE0_MME_CTRL_LO_ETF_MEM_WRAP_RM */ #define DCORE0_MME_CTRL_LO_ETF_MEM_WRAP_RM_V_SHIFT … #define DCORE0_MME_CTRL_LO_ETF_MEM_WRAP_RM_V_MASK … #endif /* ASIC_REG_DCORE0_MME_CTRL_LO_MASKS_H_ */
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