/* SPDX-License-Identifier: GPL-2.0 * * Copyright 2016-2020 HabanaLabs, Ltd. * All Rights Reserved. * */ /************************************ ** This is an auto-generated file ** ** DO NOT EDIT BELOW ** ************************************/ #ifndef ASIC_REG_DCORE0_EDMA0_CORE_MASKS_H_ #define ASIC_REG_DCORE0_EDMA0_CORE_MASKS_H_ /* ***************************************** * DCORE0_EDMA0_CORE * (Prototype: DMA_CORE) ***************************************** */ /* DCORE0_EDMA0_CORE_CFG_0 */ #define DCORE0_EDMA0_CORE_CFG_0_EN_SHIFT … #define DCORE0_EDMA0_CORE_CFG_0_EN_MASK … /* DCORE0_EDMA0_CORE_CFG_1 */ #define DCORE0_EDMA0_CORE_CFG_1_HALT_SHIFT … #define DCORE0_EDMA0_CORE_CFG_1_HALT_MASK … #define DCORE0_EDMA0_CORE_CFG_1_FLUSH_SHIFT … #define DCORE0_EDMA0_CORE_CFG_1_FLUSH_MASK … /* DCORE0_EDMA0_CORE_PROT */ #define DCORE0_EDMA0_CORE_PROT_VAL_SHIFT … #define DCORE0_EDMA0_CORE_PROT_VAL_MASK … #define DCORE0_EDMA0_CORE_PROT_ERR_VAL_SHIFT … #define DCORE0_EDMA0_CORE_PROT_ERR_VAL_MASK … /* DCORE0_EDMA0_CORE_CKG */ #define DCORE0_EDMA0_CORE_CKG_HBW_RBUF_SHIFT … #define DCORE0_EDMA0_CORE_CKG_HBW_RBUF_MASK … #define DCORE0_EDMA0_CORE_CKG_LBW_RBUF_KDMA_SHIFT … #define DCORE0_EDMA0_CORE_CKG_LBW_RBUF_KDMA_MASK … #define DCORE0_EDMA0_CORE_CKG_TE_SHIFT … #define DCORE0_EDMA0_CORE_CKG_TE_MASK … /* DCORE0_EDMA0_CORE_RD_GLBL */ #define DCORE0_EDMA0_CORE_RD_GLBL_LBW_VIA_HBW_SHIFT … #define DCORE0_EDMA0_CORE_RD_GLBL_LBW_VIA_HBW_MASK … #define DCORE0_EDMA0_CORE_RD_GLBL_HBW_FORCE_MISS_SHIFT … #define DCORE0_EDMA0_CORE_RD_GLBL_HBW_FORCE_MISS_MASK … #define DCORE0_EDMA0_CORE_RD_GLBL_LBW_FORCE_MISS_SHIFT … #define DCORE0_EDMA0_CORE_RD_GLBL_LBW_FORCE_MISS_MASK … /* DCORE0_EDMA0_CORE_RD_HBW_MAX_OUTSTAND */ #define DCORE0_EDMA0_CORE_RD_HBW_MAX_OUTSTAND_VAL_SHIFT … #define DCORE0_EDMA0_CORE_RD_HBW_MAX_OUTSTAND_VAL_MASK … /* DCORE0_EDMA0_CORE_RD_HBW_MAX_SIZE */ #define DCORE0_EDMA0_CORE_RD_HBW_MAX_SIZE_DATA_SHIFT … #define DCORE0_EDMA0_CORE_RD_HBW_MAX_SIZE_DATA_MASK … #define DCORE0_EDMA0_CORE_RD_HBW_MAX_SIZE_MD_SHIFT … #define DCORE0_EDMA0_CORE_RD_HBW_MAX_SIZE_MD_MASK … /* DCORE0_EDMA0_CORE_RD_HBW_ARCACHE */ #define DCORE0_EDMA0_CORE_RD_HBW_ARCACHE_VAL_SHIFT … #define DCORE0_EDMA0_CORE_RD_HBW_ARCACHE_VAL_MASK … /* DCORE0_EDMA0_CORE_RD_HBW_INFLIGHTS */ #define DCORE0_EDMA0_CORE_RD_HBW_INFLIGHTS_VAL_SHIFT … #define DCORE0_EDMA0_CORE_RD_HBW_INFLIGHTS_VAL_MASK … /* DCORE0_EDMA0_CORE_RD_HBW_RATE_LIM_CFG */ #define DCORE0_EDMA0_CORE_RD_HBW_RATE_LIM_CFG_TOUT_SHIFT … #define DCORE0_EDMA0_CORE_RD_HBW_RATE_LIM_CFG_TOUT_MASK … #define DCORE0_EDMA0_CORE_RD_HBW_RATE_LIM_CFG_SAT_SHIFT … #define DCORE0_EDMA0_CORE_RD_HBW_RATE_LIM_CFG_SAT_MASK … #define DCORE0_EDMA0_CORE_RD_HBW_RATE_LIM_CFG_EN_SHIFT … #define DCORE0_EDMA0_CORE_RD_HBW_RATE_LIM_CFG_EN_MASK … /* DCORE0_EDMA0_CORE_RD_LBW_MAX_OUTSTAND */ #define DCORE0_EDMA0_CORE_RD_LBW_MAX_OUTSTAND_VAL_SHIFT … #define DCORE0_EDMA0_CORE_RD_LBW_MAX_OUTSTAND_VAL_MASK … /* DCORE0_EDMA0_CORE_RD_LBW_MAX_SIZE */ #define DCORE0_EDMA0_CORE_RD_LBW_MAX_SIZE_DATA_SHIFT … #define DCORE0_EDMA0_CORE_RD_LBW_MAX_SIZE_DATA_MASK … #define DCORE0_EDMA0_CORE_RD_LBW_MAX_SIZE_MD_SHIFT … #define DCORE0_EDMA0_CORE_RD_LBW_MAX_SIZE_MD_MASK … /* DCORE0_EDMA0_CORE_RD_LBW_ARCACHE */ #define DCORE0_EDMA0_CORE_RD_LBW_ARCACHE_VAL_SHIFT … #define DCORE0_EDMA0_CORE_RD_LBW_ARCACHE_VAL_MASK … /* DCORE0_EDMA0_CORE_RD_LBW_INFLIGHTS */ #define DCORE0_EDMA0_CORE_RD_LBW_INFLIGHTS_VAL_SHIFT … #define DCORE0_EDMA0_CORE_RD_LBW_INFLIGHTS_VAL_MASK … /* DCORE0_EDMA0_CORE_RD_LBW_RATE_LIM_CFG */ #define DCORE0_EDMA0_CORE_RD_LBW_RATE_LIM_CFG_TOUT_SHIFT … #define DCORE0_EDMA0_CORE_RD_LBW_RATE_LIM_CFG_TOUT_MASK … #define DCORE0_EDMA0_CORE_RD_LBW_RATE_LIM_CFG_SAT_SHIFT … #define DCORE0_EDMA0_CORE_RD_LBW_RATE_LIM_CFG_SAT_MASK … #define DCORE0_EDMA0_CORE_RD_LBW_RATE_LIM_CFG_EN_SHIFT … #define DCORE0_EDMA0_CORE_RD_LBW_RATE_LIM_CFG_EN_MASK … /* DCORE0_EDMA0_CORE_WR_HBW_MAX_OUTSTAND */ #define DCORE0_EDMA0_CORE_WR_HBW_MAX_OUTSTAND_VAL_SHIFT … #define DCORE0_EDMA0_CORE_WR_HBW_MAX_OUTSTAND_VAL_MASK … /* DCORE0_EDMA0_CORE_WR_HBW_MAX_AWID */ #define DCORE0_EDMA0_CORE_WR_HBW_MAX_AWID_VAL_SHIFT … #define DCORE0_EDMA0_CORE_WR_HBW_MAX_AWID_VAL_MASK … /* DCORE0_EDMA0_CORE_WR_HBW_AWCACHE */ #define DCORE0_EDMA0_CORE_WR_HBW_AWCACHE_VAL_SHIFT … #define DCORE0_EDMA0_CORE_WR_HBW_AWCACHE_VAL_MASK … /* DCORE0_EDMA0_CORE_WR_HBW_INFLIGHTS */ #define DCORE0_EDMA0_CORE_WR_HBW_INFLIGHTS_VAL_SHIFT … #define DCORE0_EDMA0_CORE_WR_HBW_INFLIGHTS_VAL_MASK … /* DCORE0_EDMA0_CORE_WR_HBW_RATE_LIM_CFG */ #define DCORE0_EDMA0_CORE_WR_HBW_RATE_LIM_CFG_TOUT_SHIFT … #define DCORE0_EDMA0_CORE_WR_HBW_RATE_LIM_CFG_TOUT_MASK … #define DCORE0_EDMA0_CORE_WR_HBW_RATE_LIM_CFG_SAT_SHIFT … #define DCORE0_EDMA0_CORE_WR_HBW_RATE_LIM_CFG_SAT_MASK … #define DCORE0_EDMA0_CORE_WR_HBW_RATE_LIM_CFG_EN_SHIFT … #define DCORE0_EDMA0_CORE_WR_HBW_RATE_LIM_CFG_EN_MASK … /* DCORE0_EDMA0_CORE_WR_LBW_MAX_OUTSTAND */ #define DCORE0_EDMA0_CORE_WR_LBW_MAX_OUTSTAND_VAL_SHIFT … #define DCORE0_EDMA0_CORE_WR_LBW_MAX_OUTSTAND_VAL_MASK … /* DCORE0_EDMA0_CORE_WR_LBW_MAX_AWID */ #define DCORE0_EDMA0_CORE_WR_LBW_MAX_AWID_VAL_SHIFT … #define DCORE0_EDMA0_CORE_WR_LBW_MAX_AWID_VAL_MASK … /* DCORE0_EDMA0_CORE_WR_LBW_AWCACHE */ #define DCORE0_EDMA0_CORE_WR_LBW_AWCACHE_VAL_SHIFT … #define DCORE0_EDMA0_CORE_WR_LBW_AWCACHE_VAL_MASK … /* DCORE0_EDMA0_CORE_WR_LBW_INFLIGHTS */ #define DCORE0_EDMA0_CORE_WR_LBW_INFLIGHTS_VAL_SHIFT … #define DCORE0_EDMA0_CORE_WR_LBW_INFLIGHTS_VAL_MASK … /* DCORE0_EDMA0_CORE_WR_LBW_RATE_LIM_CFG */ #define DCORE0_EDMA0_CORE_WR_LBW_RATE_LIM_CFG_TOUT_SHIFT … #define DCORE0_EDMA0_CORE_WR_LBW_RATE_LIM_CFG_TOUT_MASK … #define DCORE0_EDMA0_CORE_WR_LBW_RATE_LIM_CFG_SAT_SHIFT … #define DCORE0_EDMA0_CORE_WR_LBW_RATE_LIM_CFG_SAT_MASK … #define DCORE0_EDMA0_CORE_WR_LBW_RATE_LIM_CFG_EN_SHIFT … #define DCORE0_EDMA0_CORE_WR_LBW_RATE_LIM_CFG_EN_MASK … /* DCORE0_EDMA0_CORE_WR_COMP_MAX_OUTSTAND */ #define DCORE0_EDMA0_CORE_WR_COMP_MAX_OUTSTAND_VAL_SHIFT … #define DCORE0_EDMA0_CORE_WR_COMP_MAX_OUTSTAND_VAL_MASK … /* DCORE0_EDMA0_CORE_WR_COMP_AWUSER */ #define DCORE0_EDMA0_CORE_WR_COMP_AWUSER_VAL_SHIFT … #define DCORE0_EDMA0_CORE_WR_COMP_AWUSER_VAL_MASK … /* DCORE0_EDMA0_CORE_ERR_CFG */ #define DCORE0_EDMA0_CORE_ERR_CFG_ERR_MSG_EN_SHIFT … #define DCORE0_EDMA0_CORE_ERR_CFG_ERR_MSG_EN_MASK … #define DCORE0_EDMA0_CORE_ERR_CFG_STOP_ON_ERR_SHIFT … #define DCORE0_EDMA0_CORE_ERR_CFG_STOP_ON_ERR_MASK … /* DCORE0_EDMA0_CORE_ERR_CAUSE */ #define DCORE0_EDMA0_CORE_ERR_CAUSE_HBW_RD_ERR_SHIFT … #define DCORE0_EDMA0_CORE_ERR_CAUSE_HBW_RD_ERR_MASK … #define DCORE0_EDMA0_CORE_ERR_CAUSE_HBW_WR_ERR_SHIFT … #define DCORE0_EDMA0_CORE_ERR_CAUSE_HBW_WR_ERR_MASK … #define DCORE0_EDMA0_CORE_ERR_CAUSE_LBW_MSG_WR_ERR_SHIFT … #define DCORE0_EDMA0_CORE_ERR_CAUSE_LBW_MSG_WR_ERR_MASK … #define DCORE0_EDMA0_CORE_ERR_CAUSE_DESC_OVF_SHIFT … #define DCORE0_EDMA0_CORE_ERR_CAUSE_DESC_OVF_MASK … #define DCORE0_EDMA0_CORE_ERR_CAUSE_LBW_RD_ERR_SHIFT … #define DCORE0_EDMA0_CORE_ERR_CAUSE_LBW_RD_ERR_MASK … #define DCORE0_EDMA0_CORE_ERR_CAUSE_LBW_WR_ERR_SHIFT … #define DCORE0_EDMA0_CORE_ERR_CAUSE_LBW_WR_ERR_MASK … #define DCORE0_EDMA0_CORE_ERR_CAUSE_TE_DESC_FIFO_OVFL_SHIFT … #define DCORE0_EDMA0_CORE_ERR_CAUSE_TE_DESC_FIFO_OVFL_MASK … #define DCORE0_EDMA0_CORE_ERR_CAUSE_LIN_DMA_COMMIT_CFG_ERR_SHIFT … #define DCORE0_EDMA0_CORE_ERR_CAUSE_LIN_DMA_COMMIT_CFG_ERR_MASK … /* DCORE0_EDMA0_CORE_ERRMSG_ADDR_LO */ #define DCORE0_EDMA0_CORE_ERRMSG_ADDR_LO_VAL_SHIFT … #define DCORE0_EDMA0_CORE_ERRMSG_ADDR_LO_VAL_MASK … /* DCORE0_EDMA0_CORE_ERRMSG_ADDR_HI */ #define DCORE0_EDMA0_CORE_ERRMSG_ADDR_HI_VAL_SHIFT … #define DCORE0_EDMA0_CORE_ERRMSG_ADDR_HI_VAL_MASK … /* DCORE0_EDMA0_CORE_ERRMSG_WDATA */ #define DCORE0_EDMA0_CORE_ERRMSG_WDATA_VAL_SHIFT … #define DCORE0_EDMA0_CORE_ERRMSG_WDATA_VAL_MASK … /* DCORE0_EDMA0_CORE_STS0 */ #define DCORE0_EDMA0_CORE_STS0_RD_REQ_CNT_SHIFT … #define DCORE0_EDMA0_CORE_STS0_RD_REQ_CNT_MASK … #define DCORE0_EDMA0_CORE_STS0_WR_REQ_CNT_SHIFT … #define DCORE0_EDMA0_CORE_STS0_WR_REQ_CNT_MASK … #define DCORE0_EDMA0_CORE_STS0_BUSY_SHIFT … #define DCORE0_EDMA0_CORE_STS0_BUSY_MASK … /* DCORE0_EDMA0_CORE_STS1 */ #define DCORE0_EDMA0_CORE_STS1_IS_HALT_SHIFT … #define DCORE0_EDMA0_CORE_STS1_IS_HALT_MASK … /* DCORE0_EDMA0_CORE_STS_RD_CTX_SEL */ #define DCORE0_EDMA0_CORE_STS_RD_CTX_SEL_VAL_SHIFT … #define DCORE0_EDMA0_CORE_STS_RD_CTX_SEL_VAL_MASK … #define DCORE0_EDMA0_CORE_STS_RD_CTX_SEL_STRIDE_SHIFT … #define DCORE0_EDMA0_CORE_STS_RD_CTX_SEL_STRIDE_MASK … /* DCORE0_EDMA0_CORE_STS_RD_CTX_SIZE */ #define DCORE0_EDMA0_CORE_STS_RD_CTX_SIZE_VAL_SHIFT … #define DCORE0_EDMA0_CORE_STS_RD_CTX_SIZE_VAL_MASK … /* DCORE0_EDMA0_CORE_STS_RD_CTX_BASE_LO */ #define DCORE0_EDMA0_CORE_STS_RD_CTX_BASE_LO_VAL_SHIFT … #define DCORE0_EDMA0_CORE_STS_RD_CTX_BASE_LO_VAL_MASK … /* DCORE0_EDMA0_CORE_STS_RD_CTX_BASE_HI */ #define DCORE0_EDMA0_CORE_STS_RD_CTX_BASE_HI_VAL_SHIFT … #define DCORE0_EDMA0_CORE_STS_RD_CTX_BASE_HI_VAL_MASK … /* DCORE0_EDMA0_CORE_STS_RD_CTX_ID */ #define DCORE0_EDMA0_CORE_STS_RD_CTX_ID_VAL_SHIFT … #define DCORE0_EDMA0_CORE_STS_RD_CTX_ID_VAL_MASK … /* DCORE0_EDMA0_CORE_STS_RD_HB_AXI_ADDR_LO */ #define DCORE0_EDMA0_CORE_STS_RD_HB_AXI_ADDR_LO_VAL_SHIFT … #define DCORE0_EDMA0_CORE_STS_RD_HB_AXI_ADDR_LO_VAL_MASK … /* DCORE0_EDMA0_CORE_STS_RD_HB_AXI_ADDR_HI */ #define DCORE0_EDMA0_CORE_STS_RD_HB_AXI_ADDR_HI_VAL_SHIFT … #define DCORE0_EDMA0_CORE_STS_RD_HB_AXI_ADDR_HI_VAL_MASK … /* DCORE0_EDMA0_CORE_STS_RD_LB_AXI_ADDR */ #define DCORE0_EDMA0_CORE_STS_RD_LB_AXI_ADDR_VAL_SHIFT … #define DCORE0_EDMA0_CORE_STS_RD_LB_AXI_ADDR_VAL_MASK … #define DCORE0_EDMA0_CORE_STS_RD_LB_AXI_ADDR_RDY_SHIFT … #define DCORE0_EDMA0_CORE_STS_RD_LB_AXI_ADDR_RDY_MASK … #define DCORE0_EDMA0_CORE_STS_RD_LB_AXI_ADDR_VLD_SHIFT … #define DCORE0_EDMA0_CORE_STS_RD_LB_AXI_ADDR_VLD_MASK … /* DCORE0_EDMA0_CORE_STS_WR_CTX_SEL */ #define DCORE0_EDMA0_CORE_STS_WR_CTX_SEL_VAL_SHIFT … #define DCORE0_EDMA0_CORE_STS_WR_CTX_SEL_VAL_MASK … #define DCORE0_EDMA0_CORE_STS_WR_CTX_SEL_STRIDE_SHIFT … #define DCORE0_EDMA0_CORE_STS_WR_CTX_SEL_STRIDE_MASK … /* DCORE0_EDMA0_CORE_STS_WR_CTX_SIZE */ #define DCORE0_EDMA0_CORE_STS_WR_CTX_SIZE_VAL_SHIFT … #define DCORE0_EDMA0_CORE_STS_WR_CTX_SIZE_VAL_MASK … /* DCORE0_EDMA0_CORE_STS_WR_CTX_BASE_LO */ #define DCORE0_EDMA0_CORE_STS_WR_CTX_BASE_LO_VAL_SHIFT … #define DCORE0_EDMA0_CORE_STS_WR_CTX_BASE_LO_VAL_MASK … /* DCORE0_EDMA0_CORE_STS_WR_CTX_BASE_HI */ #define DCORE0_EDMA0_CORE_STS_WR_CTX_BASE_HI_VAL_SHIFT … #define DCORE0_EDMA0_CORE_STS_WR_CTX_BASE_HI_VAL_MASK … /* DCORE0_EDMA0_CORE_STS_WR_CTX_ID */ #define DCORE0_EDMA0_CORE_STS_WR_CTX_ID_VAL_SHIFT … #define DCORE0_EDMA0_CORE_STS_WR_CTX_ID_VAL_MASK … /* DCORE0_EDMA0_CORE_STS_WR_HB_AXI_ADDR_LO */ #define DCORE0_EDMA0_CORE_STS_WR_HB_AXI_ADDR_LO_VAL_SHIFT … #define DCORE0_EDMA0_CORE_STS_WR_HB_AXI_ADDR_LO_VAL_MASK … #define DCORE0_EDMA0_CORE_STS_WR_HB_AXI_ADDR_LO_RDY_SHIFT … #define DCORE0_EDMA0_CORE_STS_WR_HB_AXI_ADDR_LO_RDY_MASK … #define DCORE0_EDMA0_CORE_STS_WR_HB_AXI_ADDR_LO_VLD_SHIFT … #define DCORE0_EDMA0_CORE_STS_WR_HB_AXI_ADDR_LO_VLD_MASK … /* DCORE0_EDMA0_CORE_STS_WR_HB_AXI_ADDR_HI */ #define DCORE0_EDMA0_CORE_STS_WR_HB_AXI_ADDR_HI_VAL_SHIFT … #define DCORE0_EDMA0_CORE_STS_WR_HB_AXI_ADDR_HI_VAL_MASK … #define DCORE0_EDMA0_CORE_STS_WR_HB_AXI_ADDR_HI_RDY_SHIFT … #define DCORE0_EDMA0_CORE_STS_WR_HB_AXI_ADDR_HI_RDY_MASK … #define DCORE0_EDMA0_CORE_STS_WR_HB_AXI_ADDR_HI_VLD_SHIFT … #define DCORE0_EDMA0_CORE_STS_WR_HB_AXI_ADDR_HI_VLD_MASK … /* DCORE0_EDMA0_CORE_STS_WR_LB_AXI_ADDR */ #define DCORE0_EDMA0_CORE_STS_WR_LB_AXI_ADDR_VAL_SHIFT … #define DCORE0_EDMA0_CORE_STS_WR_LB_AXI_ADDR_VAL_MASK … #define DCORE0_EDMA0_CORE_STS_WR_LB_AXI_ADDR_RDY_SHIFT … #define DCORE0_EDMA0_CORE_STS_WR_LB_AXI_ADDR_RDY_MASK … #define DCORE0_EDMA0_CORE_STS_WR_LB_AXI_ADDR_VLD_SHIFT … #define DCORE0_EDMA0_CORE_STS_WR_LB_AXI_ADDR_VLD_MASK … /* DCORE0_EDMA0_CORE_PWRLP_CFG */ #define DCORE0_EDMA0_CORE_PWRLP_CFG_GLBL_EN_SHIFT … #define DCORE0_EDMA0_CORE_PWRLP_CFG_GLBL_EN_MASK … #define DCORE0_EDMA0_CORE_PWRLP_CFG_CLR_SHIFT … #define DCORE0_EDMA0_CORE_PWRLP_CFG_CLR_MASK … /* DCORE0_EDMA0_CORE_PWRLP_STS */ #define DCORE0_EDMA0_CORE_PWRLP_STS_RLVL_SHIFT … #define DCORE0_EDMA0_CORE_PWRLP_STS_RLVL_MASK … #define DCORE0_EDMA0_CORE_PWRLP_STS_WLVL_SHIFT … #define DCORE0_EDMA0_CORE_PWRLP_STS_WLVL_MASK … #define DCORE0_EDMA0_CORE_PWRLP_STS_RCNT_SHIFT … #define DCORE0_EDMA0_CORE_PWRLP_STS_RCNT_MASK … #define DCORE0_EDMA0_CORE_PWRLP_STS_WCNT_SHIFT … #define DCORE0_EDMA0_CORE_PWRLP_STS_WCNT_MASK … #define DCORE0_EDMA0_CORE_PWRLP_STS_RFULL_SHIFT … #define DCORE0_EDMA0_CORE_PWRLP_STS_RFULL_MASK … #define DCORE0_EDMA0_CORE_PWRLP_STS_WFULL_SHIFT … #define DCORE0_EDMA0_CORE_PWRLP_STS_WFULL_MASK … /* DCORE0_EDMA0_CORE_DBG_DESC_CNT */ #define DCORE0_EDMA0_CORE_DBG_DESC_CNT_VAL_SHIFT … #define DCORE0_EDMA0_CORE_DBG_DESC_CNT_VAL_MASK … /* DCORE0_EDMA0_CORE_DBG_STS */ #define DCORE0_EDMA0_CORE_DBG_STS_RD_CTX_FULL_SHIFT … #define DCORE0_EDMA0_CORE_DBG_STS_RD_CTX_FULL_MASK … #define DCORE0_EDMA0_CORE_DBG_STS_WR_CTX_FULL_SHIFT … #define DCORE0_EDMA0_CORE_DBG_STS_WR_CTX_FULL_MASK … #define DCORE0_EDMA0_CORE_DBG_STS_WR_COMP_FULL_SHIFT … #define DCORE0_EDMA0_CORE_DBG_STS_WR_COMP_FULL_MASK … #define DCORE0_EDMA0_CORE_DBG_STS_RD_CTX_EMPTY_SHIFT … #define DCORE0_EDMA0_CORE_DBG_STS_RD_CTX_EMPTY_MASK … #define DCORE0_EDMA0_CORE_DBG_STS_WR_CTX_EMPTY_SHIFT … #define DCORE0_EDMA0_CORE_DBG_STS_WR_CTX_EMPTY_MASK … #define DCORE0_EDMA0_CORE_DBG_STS_WR_COMP_EMPTY_SHIFT … #define DCORE0_EDMA0_CORE_DBG_STS_WR_COMP_EMPTY_MASK … #define DCORE0_EDMA0_CORE_DBG_STS_TE_EMPTY_SHIFT … #define DCORE0_EDMA0_CORE_DBG_STS_TE_EMPTY_MASK … #define DCORE0_EDMA0_CORE_DBG_STS_TE_BUSY_SHIFT … #define DCORE0_EDMA0_CORE_DBG_STS_TE_BUSY_MASK … #define DCORE0_EDMA0_CORE_DBG_STS_GSKT_EMPTY_SHIFT … #define DCORE0_EDMA0_CORE_DBG_STS_GSKT_EMPTY_MASK … #define DCORE0_EDMA0_CORE_DBG_STS_GSKT_FULL_SHIFT … #define DCORE0_EDMA0_CORE_DBG_STS_GSKT_FULL_MASK … #define DCORE0_EDMA0_CORE_DBG_STS_RD_AGU_CS_SHIFT … #define DCORE0_EDMA0_CORE_DBG_STS_RD_AGU_CS_MASK … #define DCORE0_EDMA0_CORE_DBG_STS_WR_AGU_CS_SHIFT … #define DCORE0_EDMA0_CORE_DBG_STS_WR_AGU_CS_MASK … /* DCORE0_EDMA0_CORE_DBG_BUF_STS */ #define DCORE0_EDMA0_CORE_DBG_BUF_STS_HBW_FULLNESS_SHIFT … #define DCORE0_EDMA0_CORE_DBG_BUF_STS_HBW_FULLNESS_MASK … #define DCORE0_EDMA0_CORE_DBG_BUF_STS_LBW_FULLNESS_SHIFT … #define DCORE0_EDMA0_CORE_DBG_BUF_STS_LBW_FULLNESS_MASK … /* DCORE0_EDMA0_CORE_DBG_RD_DESC_ID */ #define DCORE0_EDMA0_CORE_DBG_RD_DESC_ID_VAL_SHIFT … #define DCORE0_EDMA0_CORE_DBG_RD_DESC_ID_VAL_MASK … /* DCORE0_EDMA0_CORE_DBG_WR_DESC_ID */ #define DCORE0_EDMA0_CORE_DBG_WR_DESC_ID_VAL_SHIFT … #define DCORE0_EDMA0_CORE_DBG_WR_DESC_ID_VAL_MASK … /* DCORE0_EDMA0_CORE_APB_DMA_LBW_BASE */ #define DCORE0_EDMA0_CORE_APB_DMA_LBW_BASE_VAL_SHIFT … #define DCORE0_EDMA0_CORE_APB_DMA_LBW_BASE_VAL_MASK … /* DCORE0_EDMA0_CORE_APB_MSTR_IF_LBW_BASE */ #define DCORE0_EDMA0_CORE_APB_MSTR_IF_LBW_BASE_VAL_SHIFT … #define DCORE0_EDMA0_CORE_APB_MSTR_IF_LBW_BASE_VAL_MASK … /* DCORE0_EDMA0_CORE_E2E_CRED_ASYNC_CFG */ #define DCORE0_EDMA0_CORE_E2E_CRED_ASYNC_CFG_Y_X_FORCE_SHIFT … #define DCORE0_EDMA0_CORE_E2E_CRED_ASYNC_CFG_Y_X_FORCE_MASK … #define DCORE0_EDMA0_CORE_E2E_CRED_ASYNC_CFG_FORCE_EN_SHIFT … #define DCORE0_EDMA0_CORE_E2E_CRED_ASYNC_CFG_FORCE_EN_MASK … /* DCORE0_EDMA0_CORE_DBG_APB_ENABLER */ #define DCORE0_EDMA0_CORE_DBG_APB_ENABLER_DIS_SHIFT … #define DCORE0_EDMA0_CORE_DBG_APB_ENABLER_DIS_MASK … /* DCORE0_EDMA0_CORE_L2H_CMPR_LO */ #define DCORE0_EDMA0_CORE_L2H_CMPR_LO_VAL_SHIFT … #define DCORE0_EDMA0_CORE_L2H_CMPR_LO_VAL_MASK … /* DCORE0_EDMA0_CORE_L2H_CMPR_HI */ #define DCORE0_EDMA0_CORE_L2H_CMPR_HI_VAL_SHIFT … #define DCORE0_EDMA0_CORE_L2H_CMPR_HI_VAL_MASK … /* DCORE0_EDMA0_CORE_L2H_MASK_LO */ #define DCORE0_EDMA0_CORE_L2H_MASK_LO_VAL_SHIFT … #define DCORE0_EDMA0_CORE_L2H_MASK_LO_VAL_MASK … /* DCORE0_EDMA0_CORE_L2H_MASK_HI */ #define DCORE0_EDMA0_CORE_L2H_MASK_HI_VAL_SHIFT … #define DCORE0_EDMA0_CORE_L2H_MASK_HI_VAL_MASK … /* DCORE0_EDMA0_CORE_IDLE_IND_MASK */ #define DCORE0_EDMA0_CORE_IDLE_IND_MASK_DESC_SHIFT … #define DCORE0_EDMA0_CORE_IDLE_IND_MASK_DESC_MASK … #define DCORE0_EDMA0_CORE_IDLE_IND_MASK_COMP_SHIFT … #define DCORE0_EDMA0_CORE_IDLE_IND_MASK_COMP_MASK … #define DCORE0_EDMA0_CORE_IDLE_IND_MASK_INSTAGE_SHIFT … #define DCORE0_EDMA0_CORE_IDLE_IND_MASK_INSTAGE_MASK … #define DCORE0_EDMA0_CORE_IDLE_IND_MASK_CORE_SHIFT … #define DCORE0_EDMA0_CORE_IDLE_IND_MASK_CORE_MASK … #define DCORE0_EDMA0_CORE_IDLE_IND_MASK_DESC_CNT_STS_SHIFT … #define DCORE0_EDMA0_CORE_IDLE_IND_MASK_DESC_CNT_STS_MASK … #define DCORE0_EDMA0_CORE_IDLE_IND_MASK_COMP_CNT_STS_SHIFT … #define DCORE0_EDMA0_CORE_IDLE_IND_MASK_COMP_CNT_STS_MASK … #define DCORE0_EDMA0_CORE_IDLE_IND_MASK_INSTAGE_EMPTY_SHIFT … #define DCORE0_EDMA0_CORE_IDLE_IND_MASK_INSTAGE_EMPTY_MASK … #define DCORE0_EDMA0_CORE_IDLE_IND_MASK_CORE_IDLE_STS_SHIFT … #define DCORE0_EDMA0_CORE_IDLE_IND_MASK_CORE_IDLE_STS_MASK … /* DCORE0_EDMA0_CORE_APB_ENABLER */ #define DCORE0_EDMA0_CORE_APB_ENABLER_DIS_SHIFT … #define DCORE0_EDMA0_CORE_APB_ENABLER_DIS_MASK … #endif /* ASIC_REG_DCORE0_EDMA0_CORE_MASKS_H_ */
Codebase Browser
linux