/* SPDX-License-Identifier: GPL-2.0 * * Copyright 2016-2020 HabanaLabs, Ltd. * All Rights Reserved. * */ /************************************ ** This is an auto-generated file ** ** DO NOT EDIT BELOW ** ************************************/ #ifndef ASIC_REG_DCORE0_HMMU0_STLB_MASKS_H_ #define ASIC_REG_DCORE0_HMMU0_STLB_MASKS_H_ /* ***************************************** * DCORE0_HMMU0_STLB * (Prototype: STLB) ***************************************** */ /* DCORE0_HMMU0_STLB_BUSY */ #define DCORE0_HMMU0_STLB_BUSY_BUSY_SHIFT … #define DCORE0_HMMU0_STLB_BUSY_BUSY_MASK … /* DCORE0_HMMU0_STLB_ASID */ #define DCORE0_HMMU0_STLB_ASID_ASID_SHIFT … #define DCORE0_HMMU0_STLB_ASID_ASID_MASK … /* DCORE0_HMMU0_STLB_HOP0_PA43_12 */ #define DCORE0_HMMU0_STLB_HOP0_PA43_12_HOP0_PA43_12_SHIFT … #define DCORE0_HMMU0_STLB_HOP0_PA43_12_HOP0_PA43_12_MASK … /* DCORE0_HMMU0_STLB_HOP0_PA63_44 */ #define DCORE0_HMMU0_STLB_HOP0_PA63_44_HOP0_PA63_44_SHIFT … #define DCORE0_HMMU0_STLB_HOP0_PA63_44_HOP0_PA63_44_MASK … /* DCORE0_HMMU0_STLB_CACHE_INV */ #define DCORE0_HMMU0_STLB_CACHE_INV_PRODUCER_INDEX_SHIFT … #define DCORE0_HMMU0_STLB_CACHE_INV_PRODUCER_INDEX_MASK … #define DCORE0_HMMU0_STLB_CACHE_INV_INDEX_MASK_SHIFT … #define DCORE0_HMMU0_STLB_CACHE_INV_INDEX_MASK_MASK … /* DCORE0_HMMU0_STLB_CACHE_INV_BASE_39_8 */ #define DCORE0_HMMU0_STLB_CACHE_INV_BASE_39_8_PA_SHIFT … #define DCORE0_HMMU0_STLB_CACHE_INV_BASE_39_8_PA_MASK … /* DCORE0_HMMU0_STLB_CACHE_INV_BASE_63_40 */ #define DCORE0_HMMU0_STLB_CACHE_INV_BASE_63_40_PA_SHIFT … #define DCORE0_HMMU0_STLB_CACHE_INV_BASE_63_40_PA_MASK … /* DCORE0_HMMU0_STLB_STLB_FEATURE_EN */ #define DCORE0_HMMU0_STLB_STLB_FEATURE_EN_STLB_CTRL_MULTI_PAGE_SIZE_EN_SHIFT … #define DCORE0_HMMU0_STLB_STLB_FEATURE_EN_STLB_CTRL_MULTI_PAGE_SIZE_EN_MASK … #define DCORE0_HMMU0_STLB_STLB_FEATURE_EN_MULTI_PAGE_SIZE_EN_SHIFT … #define DCORE0_HMMU0_STLB_STLB_FEATURE_EN_MULTI_PAGE_SIZE_EN_MASK … #define DCORE0_HMMU0_STLB_STLB_FEATURE_EN_LOOKUP_EN_SHIFT … #define DCORE0_HMMU0_STLB_STLB_FEATURE_EN_LOOKUP_EN_MASK … #define DCORE0_HMMU0_STLB_STLB_FEATURE_EN_BYPASS_SHIFT … #define DCORE0_HMMU0_STLB_STLB_FEATURE_EN_BYPASS_MASK … #define DCORE0_HMMU0_STLB_STLB_FEATURE_EN_BANK_STOP_SHIFT … #define DCORE0_HMMU0_STLB_STLB_FEATURE_EN_BANK_STOP_MASK … #define DCORE0_HMMU0_STLB_STLB_FEATURE_EN_TRACE_EN_SHIFT … #define DCORE0_HMMU0_STLB_STLB_FEATURE_EN_TRACE_EN_MASK … #define DCORE0_HMMU0_STLB_STLB_FEATURE_EN_FOLLOWER_EN_SHIFT … #define DCORE0_HMMU0_STLB_STLB_FEATURE_EN_FOLLOWER_EN_MASK … #define DCORE0_HMMU0_STLB_STLB_FEATURE_EN_CACHING_EN_SHIFT … #define DCORE0_HMMU0_STLB_STLB_FEATURE_EN_CACHING_EN_MASK … #define DCORE0_HMMU0_STLB_STLB_FEATURE_EN_FOLLOWING_NUM_LIMIT_SHIFT … #define DCORE0_HMMU0_STLB_STLB_FEATURE_EN_FOLLOWING_NUM_LIMIT_MASK … /* DCORE0_HMMU0_STLB_STLB_AXI_CACHE */ #define DCORE0_HMMU0_STLB_STLB_AXI_CACHE_STLB_CTRL_ARCACHE_SHIFT … #define DCORE0_HMMU0_STLB_STLB_AXI_CACHE_STLB_CTRL_ARCACHE_MASK … #define DCORE0_HMMU0_STLB_STLB_AXI_CACHE_STLB_CTRL_AWCACHE_SHIFT … #define DCORE0_HMMU0_STLB_STLB_AXI_CACHE_STLB_CTRL_AWCACHE_MASK … #define DCORE0_HMMU0_STLB_STLB_AXI_CACHE_INV_ARCACHE_SHIFT … #define DCORE0_HMMU0_STLB_STLB_AXI_CACHE_INV_ARCACHE_MASK … /* DCORE0_HMMU0_STLB_HOP_CONFIGURATION */ #define DCORE0_HMMU0_STLB_HOP_CONFIGURATION_FIRST_HOP_SHIFT … #define DCORE0_HMMU0_STLB_HOP_CONFIGURATION_FIRST_HOP_MASK … #define DCORE0_HMMU0_STLB_HOP_CONFIGURATION_FIRST_LOOKUP_HOP_SMALL_P_SHIFT … #define DCORE0_HMMU0_STLB_HOP_CONFIGURATION_FIRST_LOOKUP_HOP_SMALL_P_MASK … #define DCORE0_HMMU0_STLB_HOP_CONFIGURATION_FIRST_LOOKUP_HOP_LARGE_P_SHIFT … #define DCORE0_HMMU0_STLB_HOP_CONFIGURATION_FIRST_LOOKUP_HOP_LARGE_P_MASK … #define DCORE0_HMMU0_STLB_HOP_CONFIGURATION_LAST_HOP_SHIFT … #define DCORE0_HMMU0_STLB_HOP_CONFIGURATION_LAST_HOP_MASK … #define DCORE0_HMMU0_STLB_HOP_CONFIGURATION_FOLLOWER_HOP_SHIFT … #define DCORE0_HMMU0_STLB_HOP_CONFIGURATION_FOLLOWER_HOP_MASK … #define DCORE0_HMMU0_STLB_HOP_CONFIGURATION_ONLY_LARGE_PAGE_SHIFT … #define DCORE0_HMMU0_STLB_HOP_CONFIGURATION_ONLY_LARGE_PAGE_MASK … #define DCORE0_HMMU0_STLB_HOP_CONFIGURATION_LARGE_PAGE_INDICATION_BIT_SHIFT … #define DCORE0_HMMU0_STLB_HOP_CONFIGURATION_LARGE_PAGE_INDICATION_BIT_MASK … /* DCORE0_HMMU0_STLB_LINK_LIST_LOOKUP_MASK_63_32 */ #define DCORE0_HMMU0_STLB_LINK_LIST_LOOKUP_MASK_63_32_R_SHIFT … #define DCORE0_HMMU0_STLB_LINK_LIST_LOOKUP_MASK_63_32_R_MASK … /* DCORE0_HMMU0_STLB_LINK_LIST_LOOKUP_MASK_31_0 */ #define DCORE0_HMMU0_STLB_LINK_LIST_LOOKUP_MASK_31_0_R_SHIFT … #define DCORE0_HMMU0_STLB_LINK_LIST_LOOKUP_MASK_31_0_R_MASK … /* DCORE0_HMMU0_STLB_INV_ALL_START */ #define DCORE0_HMMU0_STLB_INV_ALL_START_R_SHIFT … #define DCORE0_HMMU0_STLB_INV_ALL_START_R_MASK … /* DCORE0_HMMU0_STLB_INV_ALL_SET */ #define DCORE0_HMMU0_STLB_INV_ALL_SET_R_SHIFT … #define DCORE0_HMMU0_STLB_INV_ALL_SET_R_MASK … /* DCORE0_HMMU0_STLB_INV_PS */ #define DCORE0_HMMU0_STLB_INV_PS_R_SHIFT … #define DCORE0_HMMU0_STLB_INV_PS_R_MASK … /* DCORE0_HMMU0_STLB_INV_CONSUMER_INDEX */ #define DCORE0_HMMU0_STLB_INV_CONSUMER_INDEX_R_SHIFT … #define DCORE0_HMMU0_STLB_INV_CONSUMER_INDEX_R_MASK … /* DCORE0_HMMU0_STLB_INV_HIT_COUNT */ #define DCORE0_HMMU0_STLB_INV_HIT_COUNT_R_SHIFT … #define DCORE0_HMMU0_STLB_INV_HIT_COUNT_R_MASK … /* DCORE0_HMMU0_STLB_INV_SET */ #define DCORE0_HMMU0_STLB_INV_SET_R_SHIFT … #define DCORE0_HMMU0_STLB_INV_SET_R_MASK … /* DCORE0_HMMU0_STLB_SRAM_INIT */ #define DCORE0_HMMU0_STLB_SRAM_INIT_BUSY_TAG_SHIFT … #define DCORE0_HMMU0_STLB_SRAM_INIT_BUSY_TAG_MASK … #define DCORE0_HMMU0_STLB_SRAM_INIT_BUSY_SLICE_SHIFT … #define DCORE0_HMMU0_STLB_SRAM_INIT_BUSY_SLICE_MASK … #define DCORE0_HMMU0_STLB_SRAM_INIT_BUSY_DATA_SHIFT … #define DCORE0_HMMU0_STLB_SRAM_INIT_BUSY_DATA_MASK … /* DCORE0_HMMU0_STLB_MEM_CACHE_INVALIDATION */ /* DCORE0_HMMU0_STLB_MEM_CACHE_INV_STATUS */ #define DCORE0_HMMU0_STLB_MEM_CACHE_INV_STATUS_INVALIDATE_DONE_SHIFT … #define DCORE0_HMMU0_STLB_MEM_CACHE_INV_STATUS_INVALIDATE_DONE_MASK … #define DCORE0_HMMU0_STLB_MEM_CACHE_INV_STATUS_CACHE_IDLE_SHIFT … #define DCORE0_HMMU0_STLB_MEM_CACHE_INV_STATUS_CACHE_IDLE_MASK … /* DCORE0_HMMU0_STLB_MEM_CACHE_BASE_38_7 */ #define DCORE0_HMMU0_STLB_MEM_CACHE_BASE_38_7_R_SHIFT … #define DCORE0_HMMU0_STLB_MEM_CACHE_BASE_38_7_R_MASK … /* DCORE0_HMMU0_STLB_MEM_CACHE_BASE_63_39 */ #define DCORE0_HMMU0_STLB_MEM_CACHE_BASE_63_39_R_SHIFT … #define DCORE0_HMMU0_STLB_MEM_CACHE_BASE_63_39_R_MASK … /* DCORE0_HMMU0_STLB_MEM_CACHE_CONFIG */ #define DCORE0_HMMU0_STLB_MEM_CACHE_CONFIG_CACHE_HOP_EN_SHIFT … #define DCORE0_HMMU0_STLB_MEM_CACHE_CONFIG_CACHE_HOP_EN_MASK … #define DCORE0_HMMU0_STLB_MEM_CACHE_CONFIG_CACHE_HOP_PREFETCH_EN_SHIFT … #define DCORE0_HMMU0_STLB_MEM_CACHE_CONFIG_CACHE_HOP_PREFETCH_EN_MASK … #define DCORE0_HMMU0_STLB_MEM_CACHE_CONFIG_BYPASS_EN_SHIFT … #define DCORE0_HMMU0_STLB_MEM_CACHE_CONFIG_BYPASS_EN_MASK … #define DCORE0_HMMU0_STLB_MEM_CACHE_CONFIG_RELEASE_INVALIDATE_SHIFT … #define DCORE0_HMMU0_STLB_MEM_CACHE_CONFIG_RELEASE_INVALIDATE_MASK … /* DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP5 */ #define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP5_MIN_SHIFT … #define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP5_MIN_MASK … #define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP5_MAX_SHIFT … #define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP5_MAX_MASK … #define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP5_MASK_SHIFT … #define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP5_MASK_MASK … /* DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP4 */ #define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP4_MIN_SHIFT … #define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP4_MIN_MASK … #define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP4_MAX_SHIFT … #define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP4_MAX_MASK … #define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP4_MASK_SHIFT … #define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP4_MASK_MASK … /* DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP3 */ #define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP3_MIN_SHIFT … #define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP3_MIN_MASK … #define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP3_MAX_SHIFT … #define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP3_MAX_MASK … #define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP3_MASK_SHIFT … #define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP3_MASK_MASK … /* DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP2 */ #define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP2_MIN_SHIFT … #define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP2_MIN_MASK … #define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP2_MAX_SHIFT … #define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP2_MAX_MASK … #define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP2_MASK_SHIFT … #define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP2_MASK_MASK … /* DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP1 */ #define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP1_MIN_SHIFT … #define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP1_MIN_MASK … #define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP1_MAX_SHIFT … #define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP1_MAX_MASK … #define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP1_MASK_SHIFT … #define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP1_MASK_MASK … /* DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP0 */ #define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP0_MIN_SHIFT … #define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP0_MIN_MASK … #define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP0_MAX_SHIFT … #define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP0_MAX_MASK … #define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP0_MASK_SHIFT … #define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP0_MASK_MASK … /* DCORE0_HMMU0_STLB_MULTI_HIT_INTERRUPT_CLR */ /* DCORE0_HMMU0_STLB_MULTI_HIT_INTERRUPT_MASK */ #define DCORE0_HMMU0_STLB_MULTI_HIT_INTERRUPT_MASK_R_SHIFT … #define DCORE0_HMMU0_STLB_MULTI_HIT_INTERRUPT_MASK_R_MASK … /* DCORE0_HMMU0_STLB_MEM_L0_CACHE_CFG */ #define DCORE0_HMMU0_STLB_MEM_L0_CACHE_CFG_PLRU_EVICTION_SHIFT … #define DCORE0_HMMU0_STLB_MEM_L0_CACHE_CFG_PLRU_EVICTION_MASK … #define DCORE0_HMMU0_STLB_MEM_L0_CACHE_CFG_CACHE_STOP_SHIFT … #define DCORE0_HMMU0_STLB_MEM_L0_CACHE_CFG_CACHE_STOP_MASK … #define DCORE0_HMMU0_STLB_MEM_L0_CACHE_CFG_INV_WRITEBACK_SHIFT … #define DCORE0_HMMU0_STLB_MEM_L0_CACHE_CFG_INV_WRITEBACK_MASK … /* DCORE0_HMMU0_STLB_MEM_READ_ARPROT */ #define DCORE0_HMMU0_STLB_MEM_READ_ARPROT_R_SHIFT … #define DCORE0_HMMU0_STLB_MEM_READ_ARPROT_R_MASK … /* DCORE0_HMMU0_STLB_RANGE_CACHE_INVALIDATION */ #define DCORE0_HMMU0_STLB_RANGE_CACHE_INVALIDATION_RANGE_INVALIDATION_ENABLE_SHIFT … #define DCORE0_HMMU0_STLB_RANGE_CACHE_INVALIDATION_RANGE_INVALIDATION_ENABLE_MASK … #define DCORE0_HMMU0_STLB_RANGE_CACHE_INVALIDATION_INVALIDATION_ASID_EN_SHIFT … #define DCORE0_HMMU0_STLB_RANGE_CACHE_INVALIDATION_INVALIDATION_ASID_EN_MASK … #define DCORE0_HMMU0_STLB_RANGE_CACHE_INVALIDATION_INVALIDATION_ASID_SHIFT … #define DCORE0_HMMU0_STLB_RANGE_CACHE_INVALIDATION_INVALIDATION_ASID_MASK … /* DCORE0_HMMU0_STLB_RANGE_INV_START_LSB */ #define DCORE0_HMMU0_STLB_RANGE_INV_START_LSB_INV_START_LSB_SHIFT … #define DCORE0_HMMU0_STLB_RANGE_INV_START_LSB_INV_START_LSB_MASK … /* DCORE0_HMMU0_STLB_RANGE_INV_START_MSB */ #define DCORE0_HMMU0_STLB_RANGE_INV_START_MSB_INV_START_MSB_SHIFT … #define DCORE0_HMMU0_STLB_RANGE_INV_START_MSB_INV_START_MSB_MASK … /* DCORE0_HMMU0_STLB_RANGE_INV_END_LSB */ #define DCORE0_HMMU0_STLB_RANGE_INV_END_LSB_INV_END_LSB_SHIFT … #define DCORE0_HMMU0_STLB_RANGE_INV_END_LSB_INV_END_LSB_MASK … /* DCORE0_HMMU0_STLB_RANGE_INV_END_MSB */ #define DCORE0_HMMU0_STLB_RANGE_INV_END_MSB_INV_END_MSB_SHIFT … #define DCORE0_HMMU0_STLB_RANGE_INV_END_MSB_INV_END_MSB_MASK … /* DCORE0_HMMU0_STLB_ASID_SCRAMBLER_CTRL */ #define DCORE0_HMMU0_STLB_ASID_SCRAMBLER_CTRL_SCRAMBLER_SCRAM_EN_SHIFT … #define DCORE0_HMMU0_STLB_ASID_SCRAMBLER_CTRL_SCRAMBLER_SCRAM_EN_MASK … /* DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_0 */ #define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_0_ASID_POLY_MATRIX_H3_SHIFT … #define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_0_ASID_POLY_MATRIX_H3_MASK … /* DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_1 */ #define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_1_ASID_POLY_MATRIX_H3_SHIFT … #define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_1_ASID_POLY_MATRIX_H3_MASK … /* DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_2 */ #define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_2_ASID_POLY_MATRIX_H3_SHIFT … #define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_2_ASID_POLY_MATRIX_H3_MASK … /* DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_3 */ #define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_3_ASID_POLY_MATRIX_H3_SHIFT … #define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_3_ASID_POLY_MATRIX_H3_MASK … /* DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_4 */ #define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_4_ASID_POLY_MATRIX_H3_SHIFT … #define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_4_ASID_POLY_MATRIX_H3_MASK … /* DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_5 */ #define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_5_ASID_POLY_MATRIX_H3_SHIFT … #define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_5_ASID_POLY_MATRIX_H3_MASK … /* DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_6 */ #define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_6_ASID_POLY_MATRIX_H3_SHIFT … #define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_6_ASID_POLY_MATRIX_H3_MASK … /* DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_7 */ #define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_7_ASID_POLY_MATRIX_H3_SHIFT … #define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_7_ASID_POLY_MATRIX_H3_MASK … /* DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_8 */ #define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_8_ASID_POLY_MATRIX_H3_SHIFT … #define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_8_ASID_POLY_MATRIX_H3_MASK … /* DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_9 */ #define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_9_ASID_POLY_MATRIX_H3_SHIFT … #define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_9_ASID_POLY_MATRIX_H3_MASK … /* DCORE0_HMMU0_STLB_ASID_SCR_POLY_MAT_H3_10 */ #define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MAT_H3_10_ASID_POLY_MATRIX_H3_SHIFT … #define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MAT_H3_10_ASID_POLY_MATRIX_H3_MASK … /* DCORE0_HMMU0_STLB_ASID_SCR_POLY_MAT_H3_11 */ #define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MAT_H3_11_ASID_POLY_MATRIX_H3_SHIFT … #define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MAT_H3_11_ASID_POLY_MATRIX_H3_MASK … /* DCORE0_HMMU0_STLB_ASID_SCR_POLY_MAT_H3_12 */ #define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MAT_H3_12_ASID_POLY_MATRIX_H3_SHIFT … #define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MAT_H3_12_ASID_POLY_MATRIX_H3_MASK … /* DCORE0_HMMU0_STLB_ASID_SCR_POLY_MAT_H3_13 */ #define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MAT_H3_13_ASID_POLY_MATRIX_H3_SHIFT … #define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MAT_H3_13_ASID_POLY_MATRIX_H3_MASK … /* DCORE0_HMMU0_STLB_ASID_SCR_POLY_MAT_H3_14 */ #define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MAT_H3_14_ASID_POLY_MATRIX_H3_SHIFT … #define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MAT_H3_14_ASID_POLY_MATRIX_H3_MASK … /* DCORE0_HMMU0_STLB_ASID_SCR_POLY_MAT_H3_15 */ #define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MAT_H3_15_ASID_POLY_MATRIX_H3_SHIFT … #define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MAT_H3_15_ASID_POLY_MATRIX_H3_MASK … /* DCORE0_HMMU0_STLB_ASID_SCR_POLY_MAT_H3_16 */ #define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MAT_H3_16_ASID_POLY_MATRIX_H3_SHIFT … #define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MAT_H3_16_ASID_POLY_MATRIX_H3_MASK … /* DCORE0_HMMU0_STLB_ASID_SCR_POLY_MAT_H3_17 */ #define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MAT_H3_17_ASID_POLY_MATRIX_H3_SHIFT … #define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MAT_H3_17_ASID_POLY_MATRIX_H3_MASK … /* DCORE0_HMMU0_STLB_ASID_SCR_POLY_MAT_H3_18 */ #define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MAT_H3_18_ASID_POLY_MATRIX_H3_SHIFT … #define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MAT_H3_18_ASID_POLY_MATRIX_H3_MASK … #endif /* ASIC_REG_DCORE0_HMMU0_STLB_MASKS_H_ */
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