/* SPDX-License-Identifier: GPL-2.0 * * Copyright 2016-2020 HabanaLabs, Ltd. * All Rights Reserved. * */ /************************************ ** This is an auto-generated file ** ** DO NOT EDIT BELOW ** ************************************/ #ifndef ASIC_REG_DCORE0_DEC0_CMD_MASKS_H_ #define ASIC_REG_DCORE0_DEC0_CMD_MASKS_H_ /* ***************************************** * DCORE0_DEC0_CMD * (Prototype: VSI_CMD) ***************************************** */ /* DCORE0_DEC0_CMD_SWREG0 */ #define DCORE0_DEC0_CMD_SWREG0_SW_HW_VERSION_SHIFT … #define DCORE0_DEC0_CMD_SWREG0_SW_HW_VERSION_MASK … #define DCORE0_DEC0_CMD_SWREG0_SW_HW_ID_SHIFT … #define DCORE0_DEC0_CMD_SWREG0_SW_HW_ID_MASK … /* DCORE0_DEC0_CMD_SWREG1 */ #define DCORE0_DEC0_CMD_SWREG1_SW_HW_BUILDDATE_SHIFT … #define DCORE0_DEC0_CMD_SWREG1_SW_HW_BUILDDATE_MASK … /* DCORE0_DEC0_CMD_SWREG2 */ #define DCORE0_DEC0_CMD_SWREG2_SW_EXT_NORM_INTR_SRC_SHIFT … #define DCORE0_DEC0_CMD_SWREG2_SW_EXT_NORM_INTR_SRC_MASK … #define DCORE0_DEC0_CMD_SWREG2_SW_EXT_ABN_INTR_SRC_SHIFT … #define DCORE0_DEC0_CMD_SWREG2_SW_EXT_ABN_INTR_SRC_MASK … /* DCORE0_DEC0_CMD_SWREG3 */ #define DCORE0_DEC0_CMD_SWREG3_SW_EXE_CMDBUF_COUNT_SHIFT … #define DCORE0_DEC0_CMD_SWREG3_SW_EXE_CMDBUF_COUNT_MASK … /* DCORE0_DEC0_CMD_SWREG4 */ #define DCORE0_DEC0_CMD_SWREG4_SW_CMD_EXE_LSB_SHIFT … #define DCORE0_DEC0_CMD_SWREG4_SW_CMD_EXE_LSB_MASK … /* DCORE0_DEC0_CMD_SWREG5 */ #define DCORE0_DEC0_CMD_SWREG5_SW_CMD_EXE_MSB_SHIFT … #define DCORE0_DEC0_CMD_SWREG5_SW_CMD_EXE_MSB_MASK … /* DCORE0_DEC0_CMD_SWREG6 */ #define DCORE0_DEC0_CMD_SWREG6_SW_AXI_TOTALARLEN_SHIFT … #define DCORE0_DEC0_CMD_SWREG6_SW_AXI_TOTALARLEN_MASK … /* DCORE0_DEC0_CMD_SWREG7 */ #define DCORE0_DEC0_CMD_SWREG7_SW_AXI_TOTALR_SHIFT … #define DCORE0_DEC0_CMD_SWREG7_SW_AXI_TOTALR_MASK … /* DCORE0_DEC0_CMD_SWREG8 */ #define DCORE0_DEC0_CMD_SWREG8_SW_AXI_TOTALAR_SHIFT … #define DCORE0_DEC0_CMD_SWREG8_SW_AXI_TOTALAR_MASK … /* DCORE0_DEC0_CMD_SWREG9 */ #define DCORE0_DEC0_CMD_SWREG9_SW_AXI_TOTALRLAST_SHIFT … #define DCORE0_DEC0_CMD_SWREG9_SW_AXI_TOTALRLAST_MASK … /* DCORE0_DEC0_CMD_SWREG10 */ #define DCORE0_DEC0_CMD_SWREG10_SW_AXI_TOTALAWLEN_SHIFT … #define DCORE0_DEC0_CMD_SWREG10_SW_AXI_TOTALAWLEN_MASK … /* DCORE0_DEC0_CMD_SWREG11 */ #define DCORE0_DEC0_CMD_SWREG11_SW_AXI_TOTALW_SHIFT … #define DCORE0_DEC0_CMD_SWREG11_SW_AXI_TOTALW_MASK … /* DCORE0_DEC0_CMD_SWREG12 */ #define DCORE0_DEC0_CMD_SWREG12_SW_AXI_TOTALAW_SHIFT … #define DCORE0_DEC0_CMD_SWREG12_SW_AXI_TOTALAW_MASK … /* DCORE0_DEC0_CMD_SWREG13 */ #define DCORE0_DEC0_CMD_SWREG13_SW_AXI_TOTALWLAST_SHIFT … #define DCORE0_DEC0_CMD_SWREG13_SW_AXI_TOTALWLAST_MASK … /* DCORE0_DEC0_CMD_SWREG14 */ #define DCORE0_DEC0_CMD_SWREG14_SW_AXI_TOTALB_SHIFT … #define DCORE0_DEC0_CMD_SWREG14_SW_AXI_TOTALB_MASK … /* DCORE0_DEC0_CMD_SWREG15 */ #define DCORE0_DEC0_CMD_SWREG15_SW_WORK_STATE_SHIFT … #define DCORE0_DEC0_CMD_SWREG15_SW_WORK_STATE_MASK … #define DCORE0_DEC0_CMD_SWREG15_RSV_SHIFT … #define DCORE0_DEC0_CMD_SWREG15_RSV_MASK … #define DCORE0_DEC0_CMD_SWREG15_SW_AXI_BREADY_SHIFT … #define DCORE0_DEC0_CMD_SWREG15_SW_AXI_BREADY_MASK … #define DCORE0_DEC0_CMD_SWREG15_SW_AXI_BVALID_SHIFT … #define DCORE0_DEC0_CMD_SWREG15_SW_AXI_BVALID_MASK … #define DCORE0_DEC0_CMD_SWREG15_SW_AXI_WREADY_SHIFT … #define DCORE0_DEC0_CMD_SWREG15_SW_AXI_WREADY_MASK … #define DCORE0_DEC0_CMD_SWREG15_SW_AXI_WVALID_SHIFT … #define DCORE0_DEC0_CMD_SWREG15_SW_AXI_WVALID_MASK … #define DCORE0_DEC0_CMD_SWREG15_SW_AXI_AWREADY_SHIFT … #define DCORE0_DEC0_CMD_SWREG15_SW_AXI_AWREADY_MASK … #define DCORE0_DEC0_CMD_SWREG15_SW_AXI_AWVALID_SHIFT … #define DCORE0_DEC0_CMD_SWREG15_SW_AXI_AWVALID_MASK … #define DCORE0_DEC0_CMD_SWREG15_SW_AXI_RREADY_SHIFT … #define DCORE0_DEC0_CMD_SWREG15_SW_AXI_RREADY_MASK … #define DCORE0_DEC0_CMD_SWREG15_SW_AXI_RVALID_SHIFT … #define DCORE0_DEC0_CMD_SWREG15_SW_AXI_RVALID_MASK … #define DCORE0_DEC0_CMD_SWREG15_SW_AXI_ARREADY_SHIFT … #define DCORE0_DEC0_CMD_SWREG15_SW_AXI_ARREADY_MASK … #define DCORE0_DEC0_CMD_SWREG15_SW_AXI_ARVALID_SHIFT … #define DCORE0_DEC0_CMD_SWREG15_SW_AXI_ARVALID_MASK … /* DCORE0_DEC0_CMD_SWREG16 */ #define DCORE0_DEC0_CMD_SWREG16_SW_START_TRIGGER_SHIFT … #define DCORE0_DEC0_CMD_SWREG16_SW_START_TRIGGER_MASK … #define DCORE0_DEC0_CMD_SWREG16_SW_RESET_ALL_SHIFT … #define DCORE0_DEC0_CMD_SWREG16_SW_RESET_ALL_MASK … #define DCORE0_DEC0_CMD_SWREG16_SW_RESET_CORE_SHIFT … #define DCORE0_DEC0_CMD_SWREG16_SW_RESET_CORE_MASK … #define DCORE0_DEC0_CMD_SWREG16_SW_ABORT_MODE_SHIFT … #define DCORE0_DEC0_CMD_SWREG16_SW_ABORT_MODE_MASK … #define DCORE0_DEC0_CMD_SWREG16_SW_CORE_CLK_GATE_DISABLE_SHIFT … #define DCORE0_DEC0_CMD_SWREG16_SW_CORE_CLK_GATE_DISABLE_MASK … #define DCORE0_DEC0_CMD_SWREG16_SW_MASTER_OUT_CLK_GATE_DISABLE_SHIFT … #define DCORE0_DEC0_CMD_SWREG16_SW_MASTER_OUT_CLK_GATE_DISABLE_MASK … #define DCORE0_DEC0_CMD_SWREG16_SW_AXI_CLK_GATE_DISABLE_SHIFT … #define DCORE0_DEC0_CMD_SWREG16_SW_AXI_CLK_GATE_DISABLE_MASK … #define DCORE0_DEC0_CMD_SWREG16_RSV_SHIFT … #define DCORE0_DEC0_CMD_SWREG16_RSV_MASK … /* DCORE0_DEC0_CMD_SWREG17 */ #define DCORE0_DEC0_CMD_SWREG17_SW_IRQ_ENDCMD_SHIFT … #define DCORE0_DEC0_CMD_SWREG17_SW_IRQ_ENDCMD_MASK … #define DCORE0_DEC0_CMD_SWREG17_SW_IRQ_BUSERR_SHIFT … #define DCORE0_DEC0_CMD_SWREG17_SW_IRQ_BUSERR_MASK … #define DCORE0_DEC0_CMD_SWREG17_SW_IRQ_TIMEOUT_SHIFT … #define DCORE0_DEC0_CMD_SWREG17_SW_IRQ_TIMEOUT_MASK … #define DCORE0_DEC0_CMD_SWREG17_SW_IRQ_CMDERR_SHIFT … #define DCORE0_DEC0_CMD_SWREG17_SW_IRQ_CMDERR_MASK … #define DCORE0_DEC0_CMD_SWREG17_SW_IRQ_ABORT_SHIFT … #define DCORE0_DEC0_CMD_SWREG17_SW_IRQ_ABORT_MASK … #define DCORE0_DEC0_CMD_SWREG17_RSV_1_SHIFT … #define DCORE0_DEC0_CMD_SWREG17_RSV_1_MASK … #define DCORE0_DEC0_CMD_SWREG17_SW_IRQ_JMP_SHIFT … #define DCORE0_DEC0_CMD_SWREG17_SW_IRQ_JMP_MASK … #define DCORE0_DEC0_CMD_SWREG17_RSV_SHIFT … #define DCORE0_DEC0_CMD_SWREG17_RSV_MASK … /* DCORE0_DEC0_CMD_SWREG18 */ #define DCORE0_DEC0_CMD_SWREG18_SW_IRQ_ENDCMD_EN_SHIFT … #define DCORE0_DEC0_CMD_SWREG18_SW_IRQ_ENDCMD_EN_MASK … #define DCORE0_DEC0_CMD_SWREG18_SW_IRQ_BUSERR_EN_SHIFT … #define DCORE0_DEC0_CMD_SWREG18_SW_IRQ_BUSERR_EN_MASK … #define DCORE0_DEC0_CMD_SWREG18_SW_IRQ_TIMEOUT_EN_SHIFT … #define DCORE0_DEC0_CMD_SWREG18_SW_IRQ_TIMEOUT_EN_MASK … #define DCORE0_DEC0_CMD_SWREG18_SW_IRQ_CMDERR_EN_SHIFT … #define DCORE0_DEC0_CMD_SWREG18_SW_IRQ_CMDERR_EN_MASK … #define DCORE0_DEC0_CMD_SWREG18_SW_IRQ_ABORT_EN_SHIFT … #define DCORE0_DEC0_CMD_SWREG18_SW_IRQ_ABORT_EN_MASK … #define DCORE0_DEC0_CMD_SWREG18_RSV_1_SHIFT … #define DCORE0_DEC0_CMD_SWREG18_RSV_1_MASK … #define DCORE0_DEC0_CMD_SWREG18_SW_IRQ_JMP_EN_SHIFT … #define DCORE0_DEC0_CMD_SWREG18_SW_IRQ_JMP_EN_MASK … #define DCORE0_DEC0_CMD_SWREG18_RSV_SHIFT … #define DCORE0_DEC0_CMD_SWREG18_RSV_MASK … /* DCORE0_DEC0_CMD_SWREG19 */ #define DCORE0_DEC0_CMD_SWREG19_SW_TIMEOUT_CYCLES_SHIFT … #define DCORE0_DEC0_CMD_SWREG19_SW_TIMEOUT_CYCLES_MASK … #define DCORE0_DEC0_CMD_SWREG19_SW_TIMEOUT_ENABLE_SHIFT … #define DCORE0_DEC0_CMD_SWREG19_SW_TIMEOUT_ENABLE_MASK … /* DCORE0_DEC0_CMD_SWREG20 */ #define DCORE0_DEC0_CMD_SWREG20_SW_CMDBUF_EXE_ADDR_LSB_SHIFT … #define DCORE0_DEC0_CMD_SWREG20_SW_CMDBUF_EXE_ADDR_LSB_MASK … /* DCORE0_DEC0_CMD_SWREG21 */ #define DCORE0_DEC0_CMD_SWREG21_SW_CMDBUF_EXE_ADDR_MSB_SHIFT … #define DCORE0_DEC0_CMD_SWREG21_SW_CMDBUF_EXE_ADDR_MSB_MASK … /* DCORE0_DEC0_CMD_SWREG22 */ #define DCORE0_DEC0_CMD_SWREG22_SW_CMDBUF_EXE_LENGTH_SHIFT … #define DCORE0_DEC0_CMD_SWREG22_SW_CMDBUF_EXE_LENGTH_MASK … #define DCORE0_DEC0_CMD_SWREG22_RSV_SHIFT … #define DCORE0_DEC0_CMD_SWREG22_RSV_MASK … /* DCORE0_DEC0_CMD_SWREG23 */ #define DCORE0_DEC0_CMD_SWREG23_SW_AXI_ID_WR_SHIFT … #define DCORE0_DEC0_CMD_SWREG23_SW_AXI_ID_WR_MASK … #define DCORE0_DEC0_CMD_SWREG23_SW_AXI_ID_RD_SHIFT … #define DCORE0_DEC0_CMD_SWREG23_SW_AXI_ID_RD_MASK … #define DCORE0_DEC0_CMD_SWREG23_SW_MAX_BURST_LEN_SHIFT … #define DCORE0_DEC0_CMD_SWREG23_SW_MAX_BURST_LEN_MASK … #define DCORE0_DEC0_CMD_SWREG23_RSV_SHIFT … #define DCORE0_DEC0_CMD_SWREG23_RSV_MASK … #define DCORE0_DEC0_CMD_SWREG23_SW_CMD_SWAP_SHIFT … #define DCORE0_DEC0_CMD_SWREG23_SW_CMD_SWAP_MASK … /* DCORE0_DEC0_CMD_SWREG24 */ #define DCORE0_DEC0_CMD_SWREG24_SW_RDY_CMDBUF_COUNT_SHIFT … #define DCORE0_DEC0_CMD_SWREG24_SW_RDY_CMDBUF_COUNT_MASK … /* DCORE0_DEC0_CMD_SWREG25 */ #define DCORE0_DEC0_CMD_SWREG25_SW_EXT_NORM_INTR_GATE_SHIFT … #define DCORE0_DEC0_CMD_SWREG25_SW_EXT_NORM_INTR_GATE_MASK … #define DCORE0_DEC0_CMD_SWREG25_SW_EXT_ABN_INTR_GATE_SHIFT … #define DCORE0_DEC0_CMD_SWREG25_SW_EXT_ABN_INTR_GATE_MASK … /* DCORE0_DEC0_CMD_SWREG26 */ #define DCORE0_DEC0_CMD_SWREG26_SW_CMDBUF_EXE_ID_SHIFT … #define DCORE0_DEC0_CMD_SWREG26_SW_CMDBUF_EXE_ID_MASK … /* DCORE0_DEC0_CMD_SWREG64 */ #define DCORE0_DEC0_CMD_SWREG64_SW_DUMMY0_SHIFT … #define DCORE0_DEC0_CMD_SWREG64_SW_DUMMY0_MASK … /* DCORE0_DEC0_CMD_SWREG65 */ #define DCORE0_DEC0_CMD_SWREG65_SW_DUMMY1_SHIFT … #define DCORE0_DEC0_CMD_SWREG65_SW_DUMMY1_MASK … /* DCORE0_DEC0_CMD_SWREG66 */ #define DCORE0_DEC0_CMD_SWREG66_SW_DUMMY2_SHIFT … #define DCORE0_DEC0_CMD_SWREG66_SW_DUMMY2_MASK … /* DCORE0_DEC0_CMD_SWREG67 */ #define DCORE0_DEC0_CMD_SWREG67_SW_DUMMY3_SHIFT … #define DCORE0_DEC0_CMD_SWREG67_SW_DUMMY3_MASK … #endif /* ASIC_REG_DCORE0_DEC0_CMD_MASKS_H_ */
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