/* SPDX-License-Identifier: GPL-2.0 * * Copyright 2016-2020 HabanaLabs, Ltd. * All Rights Reserved. * */ /************************************ ** This is an auto-generated file ** ** DO NOT EDIT BELOW ** ************************************/ #ifndef ASIC_REG_ROT0_MASKS_H_ #define ASIC_REG_ROT0_MASKS_H_ /* ***************************************** * ROT0 * (Prototype: ROTATOR) ***************************************** */ /* ROT0_KMD_MODE */ #define ROT0_KMD_MODE_EN_SHIFT … #define ROT0_KMD_MODE_EN_MASK … /* ROT0_CPL_QUEUE_EN */ #define ROT0_CPL_QUEUE_EN_Q_EN_SHIFT … #define ROT0_CPL_QUEUE_EN_Q_EN_MASK … /* ROT0_CPL_QUEUE_ADDR_L */ #define ROT0_CPL_QUEUE_ADDR_L_VAL_SHIFT … #define ROT0_CPL_QUEUE_ADDR_L_VAL_MASK … /* ROT0_CPL_QUEUE_ADDR_H */ #define ROT0_CPL_QUEUE_ADDR_H_VAL_SHIFT … #define ROT0_CPL_QUEUE_ADDR_H_VAL_MASK … /* ROT0_CPL_QUEUE_DATA */ #define ROT0_CPL_QUEUE_DATA_VAL_SHIFT … #define ROT0_CPL_QUEUE_DATA_VAL_MASK … /* ROT0_CPL_QUEUE_AWUSER */ #define ROT0_CPL_QUEUE_AWUSER_VAL_SHIFT … #define ROT0_CPL_QUEUE_AWUSER_VAL_MASK … /* ROT0_CPL_QUEUE_AXI */ #define ROT0_CPL_QUEUE_AXI_CACHE_SHIFT … #define ROT0_CPL_QUEUE_AXI_CACHE_MASK … #define ROT0_CPL_QUEUE_AXI_PROT_SHIFT … #define ROT0_CPL_QUEUE_AXI_PROT_MASK … /* ROT0_CPL_MSG_THRESHOLD */ #define ROT0_CPL_MSG_THRESHOLD_VAL_SHIFT … #define ROT0_CPL_MSG_THRESHOLD_VAL_MASK … /* ROT0_CPL_MSG_AXI */ #define ROT0_CPL_MSG_AXI_CACHE_SHIFT … #define ROT0_CPL_MSG_AXI_CACHE_MASK … #define ROT0_CPL_MSG_AXI_PROT_SHIFT … #define ROT0_CPL_MSG_AXI_PROT_MASK … /* ROT0_AXI_WB */ #define ROT0_AXI_WB_CACHE_SHIFT … #define ROT0_AXI_WB_CACHE_MASK … #define ROT0_AXI_WB_PROT_SHIFT … #define ROT0_AXI_WB_PROT_MASK … /* ROT0_ERR_CFG */ #define ROT0_ERR_CFG_STOP_ON_ERR_SHIFT … #define ROT0_ERR_CFG_STOP_ON_ERR_MASK … /* ROT0_ERR_STATUS */ #define ROT0_ERR_STATUS_ROT_HBW_RD_SHIFT … #define ROT0_ERR_STATUS_ROT_HBW_RD_MASK … #define ROT0_ERR_STATUS_ROT_HBW_WR_SHIFT … #define ROT0_ERR_STATUS_ROT_HBW_WR_MASK … #define ROT0_ERR_STATUS_QMAN_HBW_RD_SHIFT … #define ROT0_ERR_STATUS_QMAN_HBW_RD_MASK … #define ROT0_ERR_STATUS_QMAN_HBW_WR_SHIFT … #define ROT0_ERR_STATUS_QMAN_HBW_WR_MASK … #define ROT0_ERR_STATUS_ROT_LBW_WR_SHIFT … #define ROT0_ERR_STATUS_ROT_LBW_WR_MASK … /* ROT0_WBC_MAX_OUTSTANDING */ #define ROT0_WBC_MAX_OUTSTANDING_VAL_SHIFT … #define ROT0_WBC_MAX_OUTSTANDING_VAL_MASK … /* ROT0_WBC_RL */ #define ROT0_WBC_RL_SATURATION_SHIFT … #define ROT0_WBC_RL_SATURATION_MASK … #define ROT0_WBC_RL_TIMEOUT_SHIFT … #define ROT0_WBC_RL_TIMEOUT_MASK … #define ROT0_WBC_RL_RST_TOKEN_SHIFT … #define ROT0_WBC_RL_RST_TOKEN_MASK … #define ROT0_WBC_RL_RATE_LIMITER_EN_SHIFT … #define ROT0_WBC_RL_RATE_LIMITER_EN_MASK … /* ROT0_WBC_INFLIGHTS */ #define ROT0_WBC_INFLIGHTS_VAL_SHIFT … #define ROT0_WBC_INFLIGHTS_VAL_MASK … /* ROT0_WBC_INFO */ #define ROT0_WBC_INFO_EMPTY_SHIFT … #define ROT0_WBC_INFO_EMPTY_MASK … #define ROT0_WBC_INFO_AXI_IDLE_SHIFT … #define ROT0_WBC_INFO_AXI_IDLE_MASK … /* ROT0_WBC_MON */ #define ROT0_WBC_MON_CNT_SHIFT … #define ROT0_WBC_MON_CNT_MASK … #define ROT0_WBC_MON_TS_SHIFT … #define ROT0_WBC_MON_TS_MASK … #define ROT0_WBC_MON_CONTEXT_ID_SHIFT … #define ROT0_WBC_MON_CONTEXT_ID_MASK … /* ROT0_RSB_CAM_MAX_SIZE */ #define ROT0_RSB_CAM_MAX_SIZE_DATA_SHIFT … #define ROT0_RSB_CAM_MAX_SIZE_DATA_MASK … #define ROT0_RSB_CAM_MAX_SIZE_MD_SHIFT … #define ROT0_RSB_CAM_MAX_SIZE_MD_MASK … /* ROT0_RSB_CFG */ #define ROT0_RSB_CFG_CACHE_DISABLE_SHIFT … #define ROT0_RSB_CFG_CACHE_DISABLE_MASK … #define ROT0_RSB_CFG_ENABLE_CGATE_SHIFT … #define ROT0_RSB_CFG_ENABLE_CGATE_MASK … /* ROT0_RSB_MAX_OS */ #define ROT0_RSB_MAX_OS_VAL_SHIFT … #define ROT0_RSB_MAX_OS_VAL_MASK … /* ROT0_RSB_RL */ #define ROT0_RSB_RL_SATURATION_SHIFT … #define ROT0_RSB_RL_SATURATION_MASK … #define ROT0_RSB_RL_TIMEOUT_SHIFT … #define ROT0_RSB_RL_TIMEOUT_MASK … #define ROT0_RSB_RL_RST_TOKEN_SHIFT … #define ROT0_RSB_RL_RST_TOKEN_MASK … #define ROT0_RSB_RL_RATE_LIMITER_EN_SHIFT … #define ROT0_RSB_RL_RATE_LIMITER_EN_MASK … /* ROT0_RSB_INFLIGHTS */ #define ROT0_RSB_INFLIGHTS_VAL_SHIFT … #define ROT0_RSB_INFLIGHTS_VAL_MASK … /* ROT0_RSB_OCCUPANCY */ #define ROT0_RSB_OCCUPANCY_VAL_SHIFT … #define ROT0_RSB_OCCUPANCY_VAL_MASK … /* ROT0_RSB_INFO */ #define ROT0_RSB_INFO_EMPTY_SHIFT … #define ROT0_RSB_INFO_EMPTY_MASK … #define ROT0_RSB_INFO_AXI_IDLE_SHIFT … #define ROT0_RSB_INFO_AXI_IDLE_MASK … /* ROT0_RSB_MON */ #define ROT0_RSB_MON_CNT_SHIFT … #define ROT0_RSB_MON_CNT_MASK … #define ROT0_RSB_MON_TS_SHIFT … #define ROT0_RSB_MON_TS_MASK … /* ROT0_RSB_MON_CONTEXT_ID */ #define ROT0_RSB_MON_CONTEXT_ID_VAL_SHIFT … #define ROT0_RSB_MON_CONTEXT_ID_VAL_MASK … /* ROT0_MSS_HALT */ #define ROT0_MSS_HALT_VAL_SHIFT … #define ROT0_MSS_HALT_VAL_MASK … /* ROT0_MSS_SEI_STATUS */ #define ROT0_MSS_SEI_STATUS_I0_SHIFT … #define ROT0_MSS_SEI_STATUS_I0_MASK … #define ROT0_MSS_SEI_STATUS_I1_SHIFT … #define ROT0_MSS_SEI_STATUS_I1_MASK … #define ROT0_MSS_SEI_STATUS_I2_SHIFT … #define ROT0_MSS_SEI_STATUS_I2_MASK … #define ROT0_MSS_SEI_STATUS_I3_SHIFT … #define ROT0_MSS_SEI_STATUS_I3_MASK … #define ROT0_MSS_SEI_STATUS_I4_SHIFT … #define ROT0_MSS_SEI_STATUS_I4_MASK … #define ROT0_MSS_SEI_STATUS_I5_SHIFT … #define ROT0_MSS_SEI_STATUS_I5_MASK … #define ROT0_MSS_SEI_STATUS_I6_SHIFT … #define ROT0_MSS_SEI_STATUS_I6_MASK … #define ROT0_MSS_SEI_STATUS_I7_SHIFT … #define ROT0_MSS_SEI_STATUS_I7_MASK … #define ROT0_MSS_SEI_STATUS_I8_SHIFT … #define ROT0_MSS_SEI_STATUS_I8_MASK … #define ROT0_MSS_SEI_STATUS_I9_SHIFT … #define ROT0_MSS_SEI_STATUS_I9_MASK … #define ROT0_MSS_SEI_STATUS_I10_SHIFT … #define ROT0_MSS_SEI_STATUS_I10_MASK … #define ROT0_MSS_SEI_STATUS_I11_SHIFT … #define ROT0_MSS_SEI_STATUS_I11_MASK … #define ROT0_MSS_SEI_STATUS_I12_SHIFT … #define ROT0_MSS_SEI_STATUS_I12_MASK … #define ROT0_MSS_SEI_STATUS_I13_SHIFT … #define ROT0_MSS_SEI_STATUS_I13_MASK … #define ROT0_MSS_SEI_STATUS_I14_SHIFT … #define ROT0_MSS_SEI_STATUS_I14_MASK … #define ROT0_MSS_SEI_STATUS_I15_SHIFT … #define ROT0_MSS_SEI_STATUS_I15_MASK … #define ROT0_MSS_SEI_STATUS_I16_SHIFT … #define ROT0_MSS_SEI_STATUS_I16_MASK … #define ROT0_MSS_SEI_STATUS_I17_SHIFT … #define ROT0_MSS_SEI_STATUS_I17_MASK … #define ROT0_MSS_SEI_STATUS_I18_SHIFT … #define ROT0_MSS_SEI_STATUS_I18_MASK … #define ROT0_MSS_SEI_STATUS_I19_SHIFT … #define ROT0_MSS_SEI_STATUS_I19_MASK … #define ROT0_MSS_SEI_STATUS_I20_SHIFT … #define ROT0_MSS_SEI_STATUS_I20_MASK … #define ROT0_MSS_SEI_STATUS_I21_SHIFT … #define ROT0_MSS_SEI_STATUS_I21_MASK … /* ROT0_MSS_SEI_MASK */ #define ROT0_MSS_SEI_MASK_VAL_SHIFT … #define ROT0_MSS_SEI_MASK_VAL_MASK … /* ROT0_MSS_SPI_STATUS */ #define ROT0_MSS_SPI_STATUS_I0_SHIFT … #define ROT0_MSS_SPI_STATUS_I0_MASK … #define ROT0_MSS_SPI_STATUS_I1_SHIFT … #define ROT0_MSS_SPI_STATUS_I1_MASK … #define ROT0_MSS_SPI_STATUS_I2_SHIFT … #define ROT0_MSS_SPI_STATUS_I2_MASK … #define ROT0_MSS_SPI_STATUS_I3_SHIFT … #define ROT0_MSS_SPI_STATUS_I3_MASK … #define ROT0_MSS_SPI_STATUS_I4_SHIFT … #define ROT0_MSS_SPI_STATUS_I4_MASK … #define ROT0_MSS_SPI_STATUS_I5_SHIFT … #define ROT0_MSS_SPI_STATUS_I5_MASK … #define ROT0_MSS_SPI_STATUS_I6_SHIFT … #define ROT0_MSS_SPI_STATUS_I6_MASK … #define ROT0_MSS_SPI_STATUS_I7_SHIFT … #define ROT0_MSS_SPI_STATUS_I7_MASK … /* ROT0_MSS_SPI_MASK */ #define ROT0_MSS_SPI_MASK_VAL_SHIFT … #define ROT0_MSS_SPI_MASK_VAL_MASK … /* ROT0_DISABLE_PAD_CALC */ #define ROT0_DISABLE_PAD_CALC_VAL_SHIFT … #define ROT0_DISABLE_PAD_CALC_VAL_MASK … /* ROT0_QMAN_CFG */ #define ROT0_QMAN_CFG_FORCE_STOP_SHIFT … #define ROT0_QMAN_CFG_FORCE_STOP_MASK … /* ROT0_CLK_EN */ #define ROT0_CLK_EN_LBW_CFG_DIS_SHIFT … #define ROT0_CLK_EN_LBW_CFG_DIS_MASK … #define ROT0_CLK_EN_DBG_CFG_DIS_SHIFT … #define ROT0_CLK_EN_DBG_CFG_DIS_MASK … #define ROT0_CLK_EN_SB_EMPTY_MASK_SHIFT … #define ROT0_CLK_EN_SB_EMPTY_MASK_MASK … /* ROT0_MRSB_CAM_MAX_SIZE */ #define ROT0_MRSB_CAM_MAX_SIZE_DATA_SHIFT … #define ROT0_MRSB_CAM_MAX_SIZE_DATA_MASK … #define ROT0_MRSB_CAM_MAX_SIZE_MD_SHIFT … #define ROT0_MRSB_CAM_MAX_SIZE_MD_MASK … /* ROT0_MRSB_CFG */ #define ROT0_MRSB_CFG_CACHE_DISABLE_SHIFT … #define ROT0_MRSB_CFG_CACHE_DISABLE_MASK … #define ROT0_MRSB_CFG_ENABLE_CGATE_SHIFT … #define ROT0_MRSB_CFG_ENABLE_CGATE_MASK … /* ROT0_MRSB_MAX_OS */ #define ROT0_MRSB_MAX_OS_VAL_SHIFT … #define ROT0_MRSB_MAX_OS_VAL_MASK … /* ROT0_MRSB_RL */ #define ROT0_MRSB_RL_SATURATION_SHIFT … #define ROT0_MRSB_RL_SATURATION_MASK … #define ROT0_MRSB_RL_TIMEOUT_SHIFT … #define ROT0_MRSB_RL_TIMEOUT_MASK … #define ROT0_MRSB_RL_RST_TOKEN_SHIFT … #define ROT0_MRSB_RL_RST_TOKEN_MASK … #define ROT0_MRSB_RL_RATE_LIMITER_EN_SHIFT … #define ROT0_MRSB_RL_RATE_LIMITER_EN_MASK … /* ROT0_MRSB_INFLIGHTS */ #define ROT0_MRSB_INFLIGHTS_VAL_SHIFT … #define ROT0_MRSB_INFLIGHTS_VAL_MASK … /* ROT0_MRSB_OCCUPANCY */ #define ROT0_MRSB_OCCUPANCY_VAL_SHIFT … #define ROT0_MRSB_OCCUPANCY_VAL_MASK … /* ROT0_MRSB_INFO */ #define ROT0_MRSB_INFO_EMPTY_SHIFT … #define ROT0_MRSB_INFO_EMPTY_MASK … #define ROT0_MRSB_INFO_AXI_IDLE_SHIFT … #define ROT0_MRSB_INFO_AXI_IDLE_MASK … /* ROT0_MRSB_MON */ #define ROT0_MRSB_MON_CNT_SHIFT … #define ROT0_MRSB_MON_CNT_MASK … #define ROT0_MRSB_MON_TS_SHIFT … #define ROT0_MRSB_MON_TS_MASK … /* ROT0_MRSB_MON_CONTEXT_ID */ #define ROT0_MRSB_MON_CONTEXT_ID_VAL_SHIFT … #define ROT0_MRSB_MON_CONTEXT_ID_VAL_MASK … /* ROT0_MSS_STS */ #define ROT0_MSS_STS_IS_HALT_SHIFT … #define ROT0_MSS_STS_IS_HALT_MASK … #endif /* ASIC_REG_ROT0_MASKS_H_ */
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