#ifndef ASIC_REG_PMMU_HBW_STLB_MASKS_H_
#define ASIC_REG_PMMU_HBW_STLB_MASKS_H_
#define PMMU_HBW_STLB_BUSY_BUSY_SHIFT …
#define PMMU_HBW_STLB_BUSY_BUSY_MASK …
#define PMMU_HBW_STLB_ASID_ASID_SHIFT …
#define PMMU_HBW_STLB_ASID_ASID_MASK …
#define PMMU_HBW_STLB_HOP0_PA43_12_HOP0_PA43_12_SHIFT …
#define PMMU_HBW_STLB_HOP0_PA43_12_HOP0_PA43_12_MASK …
#define PMMU_HBW_STLB_HOP0_PA63_44_HOP0_PA63_44_SHIFT …
#define PMMU_HBW_STLB_HOP0_PA63_44_HOP0_PA63_44_MASK …
#define PMMU_HBW_STLB_CACHE_INV_PRODUCER_INDEX_SHIFT …
#define PMMU_HBW_STLB_CACHE_INV_PRODUCER_INDEX_MASK …
#define PMMU_HBW_STLB_CACHE_INV_INDEX_MASK_SHIFT …
#define PMMU_HBW_STLB_CACHE_INV_INDEX_MASK_MASK …
#define PMMU_HBW_STLB_CACHE_INV_BASE_39_8_PA_SHIFT …
#define PMMU_HBW_STLB_CACHE_INV_BASE_39_8_PA_MASK …
#define PMMU_HBW_STLB_CACHE_INV_BASE_63_40_PA_SHIFT …
#define PMMU_HBW_STLB_CACHE_INV_BASE_63_40_PA_MASK …
#define PMMU_HBW_STLB_STLB_FEATURE_EN_STLB_CTRL_MULTI_PAGE_SIZE_EN_SHIFT …
#define PMMU_HBW_STLB_STLB_FEATURE_EN_STLB_CTRL_MULTI_PAGE_SIZE_EN_MASK …
#define PMMU_HBW_STLB_STLB_FEATURE_EN_MULTI_PAGE_SIZE_EN_SHIFT …
#define PMMU_HBW_STLB_STLB_FEATURE_EN_MULTI_PAGE_SIZE_EN_MASK …
#define PMMU_HBW_STLB_STLB_FEATURE_EN_LOOKUP_EN_SHIFT …
#define PMMU_HBW_STLB_STLB_FEATURE_EN_LOOKUP_EN_MASK …
#define PMMU_HBW_STLB_STLB_FEATURE_EN_BYPASS_SHIFT …
#define PMMU_HBW_STLB_STLB_FEATURE_EN_BYPASS_MASK …
#define PMMU_HBW_STLB_STLB_FEATURE_EN_BANK_STOP_SHIFT …
#define PMMU_HBW_STLB_STLB_FEATURE_EN_BANK_STOP_MASK …
#define PMMU_HBW_STLB_STLB_FEATURE_EN_TRACE_EN_SHIFT …
#define PMMU_HBW_STLB_STLB_FEATURE_EN_TRACE_EN_MASK …
#define PMMU_HBW_STLB_STLB_FEATURE_EN_FOLLOWER_EN_SHIFT …
#define PMMU_HBW_STLB_STLB_FEATURE_EN_FOLLOWER_EN_MASK …
#define PMMU_HBW_STLB_STLB_FEATURE_EN_CACHING_EN_SHIFT …
#define PMMU_HBW_STLB_STLB_FEATURE_EN_CACHING_EN_MASK …
#define PMMU_HBW_STLB_STLB_FEATURE_EN_FOLLOWING_NUM_LIMIT_SHIFT …
#define PMMU_HBW_STLB_STLB_FEATURE_EN_FOLLOWING_NUM_LIMIT_MASK …
#define PMMU_HBW_STLB_STLB_AXI_CACHE_STLB_CTRL_ARCACHE_SHIFT …
#define PMMU_HBW_STLB_STLB_AXI_CACHE_STLB_CTRL_ARCACHE_MASK …
#define PMMU_HBW_STLB_STLB_AXI_CACHE_STLB_CTRL_AWCACHE_SHIFT …
#define PMMU_HBW_STLB_STLB_AXI_CACHE_STLB_CTRL_AWCACHE_MASK …
#define PMMU_HBW_STLB_STLB_AXI_CACHE_INV_ARCACHE_SHIFT …
#define PMMU_HBW_STLB_STLB_AXI_CACHE_INV_ARCACHE_MASK …
#define PMMU_HBW_STLB_HOP_CONFIGURATION_FIRST_HOP_SHIFT …
#define PMMU_HBW_STLB_HOP_CONFIGURATION_FIRST_HOP_MASK …
#define PMMU_HBW_STLB_HOP_CONFIGURATION_FIRST_LOOKUP_HOP_SMALL_P_SHIFT …
#define PMMU_HBW_STLB_HOP_CONFIGURATION_FIRST_LOOKUP_HOP_SMALL_P_MASK …
#define PMMU_HBW_STLB_HOP_CONFIGURATION_FIRST_LOOKUP_HOP_LARGE_P_SHIFT …
#define PMMU_HBW_STLB_HOP_CONFIGURATION_FIRST_LOOKUP_HOP_LARGE_P_MASK …
#define PMMU_HBW_STLB_HOP_CONFIGURATION_LAST_HOP_SHIFT …
#define PMMU_HBW_STLB_HOP_CONFIGURATION_LAST_HOP_MASK …
#define PMMU_HBW_STLB_HOP_CONFIGURATION_FOLLOWER_HOP_SHIFT …
#define PMMU_HBW_STLB_HOP_CONFIGURATION_FOLLOWER_HOP_MASK …
#define PMMU_HBW_STLB_HOP_CONFIGURATION_ONLY_LARGE_PAGE_SHIFT …
#define PMMU_HBW_STLB_HOP_CONFIGURATION_ONLY_LARGE_PAGE_MASK …
#define PMMU_HBW_STLB_HOP_CONFIGURATION_LARGE_PAGE_INDICATION_BIT_SHIFT …
#define PMMU_HBW_STLB_HOP_CONFIGURATION_LARGE_PAGE_INDICATION_BIT_MASK …
#define PMMU_HBW_STLB_LINK_LIST_LOOKUP_MASK_63_32_R_SHIFT …
#define PMMU_HBW_STLB_LINK_LIST_LOOKUP_MASK_63_32_R_MASK …
#define PMMU_HBW_STLB_LINK_LIST_LOOKUP_MASK_31_0_R_SHIFT …
#define PMMU_HBW_STLB_LINK_LIST_LOOKUP_MASK_31_0_R_MASK …
#define PMMU_HBW_STLB_INV_ALL_START_R_SHIFT …
#define PMMU_HBW_STLB_INV_ALL_START_R_MASK …
#define PMMU_HBW_STLB_INV_ALL_SET_R_SHIFT …
#define PMMU_HBW_STLB_INV_ALL_SET_R_MASK …
#define PMMU_HBW_STLB_INV_PS_R_SHIFT …
#define PMMU_HBW_STLB_INV_PS_R_MASK …
#define PMMU_HBW_STLB_INV_CONSUMER_INDEX_R_SHIFT …
#define PMMU_HBW_STLB_INV_CONSUMER_INDEX_R_MASK …
#define PMMU_HBW_STLB_INV_HIT_COUNT_R_SHIFT …
#define PMMU_HBW_STLB_INV_HIT_COUNT_R_MASK …
#define PMMU_HBW_STLB_INV_SET_R_SHIFT …
#define PMMU_HBW_STLB_INV_SET_R_MASK …
#define PMMU_HBW_STLB_SRAM_INIT_BUSY_TAG_SHIFT …
#define PMMU_HBW_STLB_SRAM_INIT_BUSY_TAG_MASK …
#define PMMU_HBW_STLB_SRAM_INIT_BUSY_SLICE_SHIFT …
#define PMMU_HBW_STLB_SRAM_INIT_BUSY_SLICE_MASK …
#define PMMU_HBW_STLB_SRAM_INIT_BUSY_DATA_SHIFT …
#define PMMU_HBW_STLB_SRAM_INIT_BUSY_DATA_MASK …
#define PMMU_HBW_STLB_MEM_CACHE_INV_STATUS_INVALIDATE_DONE_SHIFT …
#define PMMU_HBW_STLB_MEM_CACHE_INV_STATUS_INVALIDATE_DONE_MASK …
#define PMMU_HBW_STLB_MEM_CACHE_INV_STATUS_CACHE_IDLE_SHIFT …
#define PMMU_HBW_STLB_MEM_CACHE_INV_STATUS_CACHE_IDLE_MASK …
#define PMMU_HBW_STLB_MEM_CACHE_BASE_38_7_R_SHIFT …
#define PMMU_HBW_STLB_MEM_CACHE_BASE_38_7_R_MASK …
#define PMMU_HBW_STLB_MEM_CACHE_BASE_63_39_R_SHIFT …
#define PMMU_HBW_STLB_MEM_CACHE_BASE_63_39_R_MASK …
#define PMMU_HBW_STLB_MEM_CACHE_CONFIG_CACHE_HOP_EN_SHIFT …
#define PMMU_HBW_STLB_MEM_CACHE_CONFIG_CACHE_HOP_EN_MASK …
#define PMMU_HBW_STLB_MEM_CACHE_CONFIG_CACHE_HOP_PREFETCH_EN_SHIFT …
#define PMMU_HBW_STLB_MEM_CACHE_CONFIG_CACHE_HOP_PREFETCH_EN_MASK …
#define PMMU_HBW_STLB_MEM_CACHE_CONFIG_BYPASS_EN_SHIFT …
#define PMMU_HBW_STLB_MEM_CACHE_CONFIG_BYPASS_EN_MASK …
#define PMMU_HBW_STLB_MEM_CACHE_CONFIG_RELEASE_INVALIDATE_SHIFT …
#define PMMU_HBW_STLB_MEM_CACHE_CONFIG_RELEASE_INVALIDATE_MASK …
#define PMMU_HBW_STLB_SET_THRESHOLD_HOP5_MIN_SHIFT …
#define PMMU_HBW_STLB_SET_THRESHOLD_HOP5_MIN_MASK …
#define PMMU_HBW_STLB_SET_THRESHOLD_HOP5_MAX_SHIFT …
#define PMMU_HBW_STLB_SET_THRESHOLD_HOP5_MAX_MASK …
#define PMMU_HBW_STLB_SET_THRESHOLD_HOP5_MASK_SHIFT …
#define PMMU_HBW_STLB_SET_THRESHOLD_HOP5_MASK_MASK …
#define PMMU_HBW_STLB_SET_THRESHOLD_HOP4_MIN_SHIFT …
#define PMMU_HBW_STLB_SET_THRESHOLD_HOP4_MIN_MASK …
#define PMMU_HBW_STLB_SET_THRESHOLD_HOP4_MAX_SHIFT …
#define PMMU_HBW_STLB_SET_THRESHOLD_HOP4_MAX_MASK …
#define PMMU_HBW_STLB_SET_THRESHOLD_HOP4_MASK_SHIFT …
#define PMMU_HBW_STLB_SET_THRESHOLD_HOP4_MASK_MASK …
#define PMMU_HBW_STLB_SET_THRESHOLD_HOP3_MIN_SHIFT …
#define PMMU_HBW_STLB_SET_THRESHOLD_HOP3_MIN_MASK …
#define PMMU_HBW_STLB_SET_THRESHOLD_HOP3_MAX_SHIFT …
#define PMMU_HBW_STLB_SET_THRESHOLD_HOP3_MAX_MASK …
#define PMMU_HBW_STLB_SET_THRESHOLD_HOP3_MASK_SHIFT …
#define PMMU_HBW_STLB_SET_THRESHOLD_HOP3_MASK_MASK …
#define PMMU_HBW_STLB_SET_THRESHOLD_HOP2_MIN_SHIFT …
#define PMMU_HBW_STLB_SET_THRESHOLD_HOP2_MIN_MASK …
#define PMMU_HBW_STLB_SET_THRESHOLD_HOP2_MAX_SHIFT …
#define PMMU_HBW_STLB_SET_THRESHOLD_HOP2_MAX_MASK …
#define PMMU_HBW_STLB_SET_THRESHOLD_HOP2_MASK_SHIFT …
#define PMMU_HBW_STLB_SET_THRESHOLD_HOP2_MASK_MASK …
#define PMMU_HBW_STLB_SET_THRESHOLD_HOP1_MIN_SHIFT …
#define PMMU_HBW_STLB_SET_THRESHOLD_HOP1_MIN_MASK …
#define PMMU_HBW_STLB_SET_THRESHOLD_HOP1_MAX_SHIFT …
#define PMMU_HBW_STLB_SET_THRESHOLD_HOP1_MAX_MASK …
#define PMMU_HBW_STLB_SET_THRESHOLD_HOP1_MASK_SHIFT …
#define PMMU_HBW_STLB_SET_THRESHOLD_HOP1_MASK_MASK …
#define PMMU_HBW_STLB_SET_THRESHOLD_HOP0_MIN_SHIFT …
#define PMMU_HBW_STLB_SET_THRESHOLD_HOP0_MIN_MASK …
#define PMMU_HBW_STLB_SET_THRESHOLD_HOP0_MAX_SHIFT …
#define PMMU_HBW_STLB_SET_THRESHOLD_HOP0_MAX_MASK …
#define PMMU_HBW_STLB_SET_THRESHOLD_HOP0_MASK_SHIFT …
#define PMMU_HBW_STLB_SET_THRESHOLD_HOP0_MASK_MASK …
#define PMMU_HBW_STLB_MULTI_HIT_INTERRUPT_MASK_R_SHIFT …
#define PMMU_HBW_STLB_MULTI_HIT_INTERRUPT_MASK_R_MASK …
#define PMMU_HBW_STLB_MEM_L0_CACHE_CFG_PLRU_EVICTION_SHIFT …
#define PMMU_HBW_STLB_MEM_L0_CACHE_CFG_PLRU_EVICTION_MASK …
#define PMMU_HBW_STLB_MEM_L0_CACHE_CFG_CACHE_STOP_SHIFT …
#define PMMU_HBW_STLB_MEM_L0_CACHE_CFG_CACHE_STOP_MASK …
#define PMMU_HBW_STLB_MEM_L0_CACHE_CFG_INV_WRITEBACK_SHIFT …
#define PMMU_HBW_STLB_MEM_L0_CACHE_CFG_INV_WRITEBACK_MASK …
#define PMMU_HBW_STLB_MEM_READ_ARPROT_R_SHIFT …
#define PMMU_HBW_STLB_MEM_READ_ARPROT_R_MASK …
#define PMMU_HBW_STLB_RANGE_CACHE_INVALIDATION_RANGE_INVALIDATION_ENABLE_SHIFT …
#define PMMU_HBW_STLB_RANGE_CACHE_INVALIDATION_RANGE_INVALIDATION_ENABLE_MASK …
#define PMMU_HBW_STLB_RANGE_CACHE_INVALIDATION_INVALIDATION_ASID_EN_SHIFT …
#define PMMU_HBW_STLB_RANGE_CACHE_INVALIDATION_INVALIDATION_ASID_EN_MASK …
#define PMMU_HBW_STLB_RANGE_CACHE_INVALIDATION_INVALIDATION_ASID_SHIFT …
#define PMMU_HBW_STLB_RANGE_CACHE_INVALIDATION_INVALIDATION_ASID_MASK …
#define PMMU_HBW_STLB_RANGE_INV_START_LSB_INV_START_LSB_SHIFT …
#define PMMU_HBW_STLB_RANGE_INV_START_LSB_INV_START_LSB_MASK …
#define PMMU_HBW_STLB_RANGE_INV_START_MSB_INV_START_MSB_SHIFT …
#define PMMU_HBW_STLB_RANGE_INV_START_MSB_INV_START_MSB_MASK …
#define PMMU_HBW_STLB_RANGE_INV_END_LSB_INV_END_LSB_SHIFT …
#define PMMU_HBW_STLB_RANGE_INV_END_LSB_INV_END_LSB_MASK …
#define PMMU_HBW_STLB_RANGE_INV_END_MSB_INV_END_MSB_SHIFT …
#define PMMU_HBW_STLB_RANGE_INV_END_MSB_INV_END_MSB_MASK …
#define PMMU_HBW_STLB_ASID_SCRAMBLER_CTRL_SCRAMBLER_SCRAM_EN_SHIFT …
#define PMMU_HBW_STLB_ASID_SCRAMBLER_CTRL_SCRAMBLER_SCRAM_EN_MASK …
#define PMMU_HBW_STLB_ASID_SCR_POLY_MATRIX_H3_0_ASID_POLY_MATRIX_H3_SHIFT …
#define PMMU_HBW_STLB_ASID_SCR_POLY_MATRIX_H3_0_ASID_POLY_MATRIX_H3_MASK …
#define PMMU_HBW_STLB_ASID_SCR_POLY_MATRIX_H3_1_ASID_POLY_MATRIX_H3_SHIFT …
#define PMMU_HBW_STLB_ASID_SCR_POLY_MATRIX_H3_1_ASID_POLY_MATRIX_H3_MASK …
#define PMMU_HBW_STLB_ASID_SCR_POLY_MATRIX_H3_2_ASID_POLY_MATRIX_H3_SHIFT …
#define PMMU_HBW_STLB_ASID_SCR_POLY_MATRIX_H3_2_ASID_POLY_MATRIX_H3_MASK …
#define PMMU_HBW_STLB_ASID_SCR_POLY_MATRIX_H3_3_ASID_POLY_MATRIX_H3_SHIFT …
#define PMMU_HBW_STLB_ASID_SCR_POLY_MATRIX_H3_3_ASID_POLY_MATRIX_H3_MASK …
#define PMMU_HBW_STLB_ASID_SCR_POLY_MATRIX_H3_4_ASID_POLY_MATRIX_H3_SHIFT …
#define PMMU_HBW_STLB_ASID_SCR_POLY_MATRIX_H3_4_ASID_POLY_MATRIX_H3_MASK …
#define PMMU_HBW_STLB_ASID_SCR_POLY_MATRIX_H3_5_ASID_POLY_MATRIX_H3_SHIFT …
#define PMMU_HBW_STLB_ASID_SCR_POLY_MATRIX_H3_5_ASID_POLY_MATRIX_H3_MASK …
#define PMMU_HBW_STLB_ASID_SCR_POLY_MATRIX_H3_6_ASID_POLY_MATRIX_H3_SHIFT …
#define PMMU_HBW_STLB_ASID_SCR_POLY_MATRIX_H3_6_ASID_POLY_MATRIX_H3_MASK …
#define PMMU_HBW_STLB_ASID_SCR_POLY_MATRIX_H3_7_ASID_POLY_MATRIX_H3_SHIFT …
#define PMMU_HBW_STLB_ASID_SCR_POLY_MATRIX_H3_7_ASID_POLY_MATRIX_H3_MASK …
#define PMMU_HBW_STLB_ASID_SCR_POLY_MATRIX_H3_8_ASID_POLY_MATRIX_H3_SHIFT …
#define PMMU_HBW_STLB_ASID_SCR_POLY_MATRIX_H3_8_ASID_POLY_MATRIX_H3_MASK …
#define PMMU_HBW_STLB_ASID_SCR_POLY_MATRIX_H3_9_ASID_POLY_MATRIX_H3_SHIFT …
#define PMMU_HBW_STLB_ASID_SCR_POLY_MATRIX_H3_9_ASID_POLY_MATRIX_H3_MASK …
#define PMMU_HBW_STLB_ASID_SCR_POLY_MAT_H3_10_ASID_POLY_MATRIX_H3_SHIFT …
#define PMMU_HBW_STLB_ASID_SCR_POLY_MAT_H3_10_ASID_POLY_MATRIX_H3_MASK …
#define PMMU_HBW_STLB_ASID_SCR_POLY_MAT_H3_11_ASID_POLY_MATRIX_H3_SHIFT …
#define PMMU_HBW_STLB_ASID_SCR_POLY_MAT_H3_11_ASID_POLY_MATRIX_H3_MASK …
#define PMMU_HBW_STLB_ASID_SCR_POLY_MAT_H3_12_ASID_POLY_MATRIX_H3_SHIFT …
#define PMMU_HBW_STLB_ASID_SCR_POLY_MAT_H3_12_ASID_POLY_MATRIX_H3_MASK …
#define PMMU_HBW_STLB_ASID_SCR_POLY_MAT_H3_13_ASID_POLY_MATRIX_H3_SHIFT …
#define PMMU_HBW_STLB_ASID_SCR_POLY_MAT_H3_13_ASID_POLY_MATRIX_H3_MASK …
#define PMMU_HBW_STLB_ASID_SCR_POLY_MAT_H3_14_ASID_POLY_MATRIX_H3_SHIFT …
#define PMMU_HBW_STLB_ASID_SCR_POLY_MAT_H3_14_ASID_POLY_MATRIX_H3_MASK …
#define PMMU_HBW_STLB_ASID_SCR_POLY_MAT_H3_15_ASID_POLY_MATRIX_H3_SHIFT …
#define PMMU_HBW_STLB_ASID_SCR_POLY_MAT_H3_15_ASID_POLY_MATRIX_H3_MASK …
#define PMMU_HBW_STLB_ASID_SCR_POLY_MAT_H3_16_ASID_POLY_MATRIX_H3_SHIFT …
#define PMMU_HBW_STLB_ASID_SCR_POLY_MAT_H3_16_ASID_POLY_MATRIX_H3_MASK …
#define PMMU_HBW_STLB_ASID_SCR_POLY_MAT_H3_17_ASID_POLY_MATRIX_H3_SHIFT …
#define PMMU_HBW_STLB_ASID_SCR_POLY_MAT_H3_17_ASID_POLY_MATRIX_H3_MASK …
#define PMMU_HBW_STLB_ASID_SCR_POLY_MAT_H3_18_ASID_POLY_MATRIX_H3_SHIFT …
#define PMMU_HBW_STLB_ASID_SCR_POLY_MAT_H3_18_ASID_POLY_MATRIX_H3_MASK …
#endif