linux/drivers/accel/habanalabs/include/gaudi2/asic_reg/psoc_etr_masks.h

/* SPDX-License-Identifier: GPL-2.0
 *
 * Copyright 2016-2020 HabanaLabs, Ltd.
 * All Rights Reserved.
 *
 */

/************************************
 ** This is an auto-generated file **
 **       DO NOT EDIT BELOW        **
 ************************************/

#ifndef ASIC_REG_PSOC_ETR_MASKS_H_
#define ASIC_REG_PSOC_ETR_MASKS_H_

/*
 *****************************************
 *   PSOC_ETR
 *   (Prototype: ETR)
 *****************************************
 */

/* PSOC_ETR_RSZ */
#define PSOC_ETR_RSZ_RSZ_ETR_SHIFT
#define PSOC_ETR_RSZ_RSZ_ETR_MASK

/* PSOC_ETR_STS */
#define PSOC_ETR_STS_FULL_SHIFT
#define PSOC_ETR_STS_FULL_MASK
#define PSOC_ETR_STS_TRIGGERED_SHIFT
#define PSOC_ETR_STS_TRIGGERED_MASK
#define PSOC_ETR_STS_TMCREADY_SHIFT
#define PSOC_ETR_STS_TMCREADY_MASK
#define PSOC_ETR_STS_FTEMPTY_SHIFT
#define PSOC_ETR_STS_FTEMPTY_MASK
#define PSOC_ETR_STS_EMPTY_SHIFT
#define PSOC_ETR_STS_EMPTY_MASK
#define PSOC_ETR_STS_MEMERR_SHIFT
#define PSOC_ETR_STS_MEMERR_MASK

/* PSOC_ETR_RRD */
#define PSOC_ETR_RRD_RRD_SHIFT
#define PSOC_ETR_RRD_RRD_MASK

/* PSOC_ETR_RRP */
#define PSOC_ETR_RRP_RRP_SHIFT
#define PSOC_ETR_RRP_RRP_MASK

/* PSOC_ETR_RWP */
#define PSOC_ETR_RWP_RWP_SHIFT
#define PSOC_ETR_RWP_RWP_MASK

/* PSOC_ETR_TRG */
#define PSOC_ETR_TRG_TRG_SHIFT
#define PSOC_ETR_TRG_TRG_MASK

/* PSOC_ETR_CTL */
#define PSOC_ETR_CTL_TRACECAPTEN_SHIFT
#define PSOC_ETR_CTL_TRACECAPTEN_MASK

/* PSOC_ETR_RWD */
#define PSOC_ETR_RWD_RWD_SHIFT
#define PSOC_ETR_RWD_RWD_MASK

/* PSOC_ETR_MODE */
#define PSOC_ETR_MODE_MODE_SHIFT
#define PSOC_ETR_MODE_MODE_MASK

/* PSOC_ETR_LBUFLEVEL */
#define PSOC_ETR_LBUFLEVEL_LBUFLEVEL_SHIFT
#define PSOC_ETR_LBUFLEVEL_LBUFLEVEL_MASK

/* PSOC_ETR_CBUFLEVEL */
#define PSOC_ETR_CBUFLEVEL_CBUFLEVEL_SHIFT
#define PSOC_ETR_CBUFLEVEL_CBUFLEVEL_MASK

/* PSOC_ETR_BUFWM */
#define PSOC_ETR_BUFWM_BUFWM_SHIFT
#define PSOC_ETR_BUFWM_BUFWM_MASK

/* PSOC_ETR_RRPHI */
#define PSOC_ETR_RRPHI_RRPHI_SHIFT
#define PSOC_ETR_RRPHI_RRPHI_MASK

/* PSOC_ETR_RWPHI */
#define PSOC_ETR_RWPHI_RWPHI_SHIFT
#define PSOC_ETR_RWPHI_RWPHI_MASK

/* PSOC_ETR_AXICTL */
#define PSOC_ETR_AXICTL_PROTCTRLBIT0_SHIFT
#define PSOC_ETR_AXICTL_PROTCTRLBIT0_MASK
#define PSOC_ETR_AXICTL_PROTCTRLBIT1_SHIFT
#define PSOC_ETR_AXICTL_PROTCTRLBIT1_MASK
#define PSOC_ETR_AXICTL_CACHECTRLBIT0_SHIFT
#define PSOC_ETR_AXICTL_CACHECTRLBIT0_MASK
#define PSOC_ETR_AXICTL_CACHECTRLBIT1_SHIFT
#define PSOC_ETR_AXICTL_CACHECTRLBIT1_MASK
#define PSOC_ETR_AXICTL_CACHECTRLBIT2_SHIFT
#define PSOC_ETR_AXICTL_CACHECTRLBIT2_MASK
#define PSOC_ETR_AXICTL_CACHECTRLBIT3_SHIFT
#define PSOC_ETR_AXICTL_CACHECTRLBIT3_MASK
#define PSOC_ETR_AXICTL_SCATTERGATHERMODE_SHIFT
#define PSOC_ETR_AXICTL_SCATTERGATHERMODE_MASK
#define PSOC_ETR_AXICTL_WRBURSTLEN_SHIFT
#define PSOC_ETR_AXICTL_WRBURSTLEN_MASK

/* PSOC_ETR_DBALO */
#define PSOC_ETR_DBALO_BUFADDRLO_SHIFT
#define PSOC_ETR_DBALO_BUFADDRLO_MASK

/* PSOC_ETR_DBAHI */
#define PSOC_ETR_DBAHI_BUFADDRHI_SHIFT
#define PSOC_ETR_DBAHI_BUFADDRHI_MASK

/* PSOC_ETR_FFSR */
#define PSOC_ETR_FFSR_FLINPROG_SHIFT
#define PSOC_ETR_FFSR_FLINPROG_MASK
#define PSOC_ETR_FFSR_FTSTOPPED_SHIFT
#define PSOC_ETR_FFSR_FTSTOPPED_MASK

/* PSOC_ETR_FFCR */
#define PSOC_ETR_FFCR_ENFT_SHIFT
#define PSOC_ETR_FFCR_ENFT_MASK
#define PSOC_ETR_FFCR_ENTI_SHIFT
#define PSOC_ETR_FFCR_ENTI_MASK
#define PSOC_ETR_FFCR_FONFLIN_SHIFT
#define PSOC_ETR_FFCR_FONFLIN_MASK
#define PSOC_ETR_FFCR_FONTRIGEVT_SHIFT
#define PSOC_ETR_FFCR_FONTRIGEVT_MASK
#define PSOC_ETR_FFCR_FLUSHMAN_SHIFT
#define PSOC_ETR_FFCR_FLUSHMAN_MASK
#define PSOC_ETR_FFCR_TRIGONTRIGIN_SHIFT
#define PSOC_ETR_FFCR_TRIGONTRIGIN_MASK
#define PSOC_ETR_FFCR_TRIGONTRIGEVT_SHIFT
#define PSOC_ETR_FFCR_TRIGONTRIGEVT_MASK
#define PSOC_ETR_FFCR_TRIGONFL_SHIFT
#define PSOC_ETR_FFCR_TRIGONFL_MASK
#define PSOC_ETR_FFCR_STOPONFL_SHIFT
#define PSOC_ETR_FFCR_STOPONFL_MASK
#define PSOC_ETR_FFCR_STOPONTRIGEVT_SHIFT
#define PSOC_ETR_FFCR_STOPONTRIGEVT_MASK

/* PSOC_ETR_PSCR */
#define PSOC_ETR_PSCR_PSCOUNT_SHIFT
#define PSOC_ETR_PSCR_PSCOUNT_MASK

/* PSOC_ETR_ITMISCOP0 */
#define PSOC_ETR_ITMISCOP0_ACQCOMP_SHIFT
#define PSOC_ETR_ITMISCOP0_ACQCOMP_MASK
#define PSOC_ETR_ITMISCOP0_FULL_SHIFT
#define PSOC_ETR_ITMISCOP0_FULL_MASK

/* PSOC_ETR_ITTRFLIN */
#define PSOC_ETR_ITTRFLIN_TRIGIN_SHIFT
#define PSOC_ETR_ITTRFLIN_TRIGIN_MASK
#define PSOC_ETR_ITTRFLIN_FLUSHIN_SHIFT
#define PSOC_ETR_ITTRFLIN_FLUSHIN_MASK

/* PSOC_ETR_ITATBDATA0 */
#define PSOC_ETR_ITATBDATA0_ATDATASBIT0_SHIFT
#define PSOC_ETR_ITATBDATA0_ATDATASBIT0_MASK
#define PSOC_ETR_ITATBDATA0_ATDATASBIT7_SHIFT
#define PSOC_ETR_ITATBDATA0_ATDATASBIT7_MASK
#define PSOC_ETR_ITATBDATA0_ATDATASBIT15_SHIFT
#define PSOC_ETR_ITATBDATA0_ATDATASBIT15_MASK
#define PSOC_ETR_ITATBDATA0_ATDATASBIT23_SHIFT
#define PSOC_ETR_ITATBDATA0_ATDATASBIT23_MASK
#define PSOC_ETR_ITATBDATA0_ATDATASBIT31_SHIFT
#define PSOC_ETR_ITATBDATA0_ATDATASBIT31_MASK
#define PSOC_ETR_ITATBDATA0_ATDATASBIT39_SHIFT
#define PSOC_ETR_ITATBDATA0_ATDATASBIT39_MASK
#define PSOC_ETR_ITATBDATA0_ATDATASBIT47_SHIFT
#define PSOC_ETR_ITATBDATA0_ATDATASBIT47_MASK
#define PSOC_ETR_ITATBDATA0_ATDATASBIT55_SHIFT
#define PSOC_ETR_ITATBDATA0_ATDATASBIT55_MASK
#define PSOC_ETR_ITATBDATA0_ATDATASBIT63_SHIFT
#define PSOC_ETR_ITATBDATA0_ATDATASBIT63_MASK

/* PSOC_ETR_ITATBCTR2 */
#define PSOC_ETR_ITATBCTR2_ATREADYS_SHIFT
#define PSOC_ETR_ITATBCTR2_ATREADYS_MASK
#define PSOC_ETR_ITATBCTR2_AFVALIDS_SHIFT
#define PSOC_ETR_ITATBCTR2_AFVALIDS_MASK
#define PSOC_ETR_ITATBCTR2_SYNCREQS_SHIFT
#define PSOC_ETR_ITATBCTR2_SYNCREQS_MASK

/* PSOC_ETR_ITATBCTR1 */
#define PSOC_ETR_ITATBCTR1_ATIDS_SHIFT
#define PSOC_ETR_ITATBCTR1_ATIDS_MASK

/* PSOC_ETR_ITATBCTR0 */
#define PSOC_ETR_ITATBCTR0_ATVALIDS_SHIFT
#define PSOC_ETR_ITATBCTR0_ATVALIDS_MASK
#define PSOC_ETR_ITATBCTR0_AFREADYS_SHIFT
#define PSOC_ETR_ITATBCTR0_AFREADYS_MASK
#define PSOC_ETR_ITATBCTR0_ATBYTESS_SHIFT
#define PSOC_ETR_ITATBCTR0_ATBYTESS_MASK

/* PSOC_ETR_ITCTRL */
#define PSOC_ETR_ITCTRL_INTEGRATION_MODE_SHIFT
#define PSOC_ETR_ITCTRL_INTEGRATION_MODE_MASK

/* PSOC_ETR_CLAIMSET */
#define PSOC_ETR_CLAIMSET_CLAIMSET_SHIFT
#define PSOC_ETR_CLAIMSET_CLAIMSET_MASK

/* PSOC_ETR_CLAIMCLR */
#define PSOC_ETR_CLAIMCLR_CLAIMCLR_SHIFT
#define PSOC_ETR_CLAIMCLR_CLAIMCLR_MASK

/* PSOC_ETR_LAR */
#define PSOC_ETR_LAR_ACCESS_W_SHIFT
#define PSOC_ETR_LAR_ACCESS_W_MASK

/* PSOC_ETR_LSR */
#define PSOC_ETR_LSR_LOCKEXIST_SHIFT
#define PSOC_ETR_LSR_LOCKEXIST_MASK
#define PSOC_ETR_LSR_LOCKGRANT_SHIFT
#define PSOC_ETR_LSR_LOCKGRANT_MASK
#define PSOC_ETR_LSR_LOCKTYPE_SHIFT
#define PSOC_ETR_LSR_LOCKTYPE_MASK

/* PSOC_ETR_AUTHSTATUS */
#define PSOC_ETR_AUTHSTATUS_NSID_SHIFT
#define PSOC_ETR_AUTHSTATUS_NSID_MASK
#define PSOC_ETR_AUTHSTATUS_NSNID_SHIFT
#define PSOC_ETR_AUTHSTATUS_NSNID_MASK
#define PSOC_ETR_AUTHSTATUS_SID_SHIFT
#define PSOC_ETR_AUTHSTATUS_SID_MASK
#define PSOC_ETR_AUTHSTATUS_SNID_SHIFT
#define PSOC_ETR_AUTHSTATUS_SNID_MASK

/* PSOC_ETR_DEVID */
#define PSOC_ETR_DEVID_ATBINPORTCOUNT_SHIFT
#define PSOC_ETR_DEVID_ATBINPORTCOUNT_MASK
#define PSOC_ETR_DEVID_CLKSCHEME_SHIFT
#define PSOC_ETR_DEVID_CLKSCHEME_MASK
#define PSOC_ETR_DEVID_CONFIGTYPE_SHIFT
#define PSOC_ETR_DEVID_CONFIGTYPE_MASK
#define PSOC_ETR_DEVID_MEMWIDTH_SHIFT
#define PSOC_ETR_DEVID_MEMWIDTH_MASK
#define PSOC_ETR_DEVID_WBUF_DEPTH_SHIFT
#define PSOC_ETR_DEVID_WBUF_DEPTH_MASK

/* PSOC_ETR_DEVTYPE */
#define PSOC_ETR_DEVTYPE_MAJOR_TYPE_SHIFT
#define PSOC_ETR_DEVTYPE_MAJOR_TYPE_MASK
#define PSOC_ETR_DEVTYPE_SUB_TYPE_SHIFT
#define PSOC_ETR_DEVTYPE_SUB_TYPE_MASK

/* PSOC_ETR_PERIPHID4 */
#define PSOC_ETR_PERIPHID4_JEP106_CONT_SHIFT
#define PSOC_ETR_PERIPHID4_JEP106_CONT_MASK
#define PSOC_ETR_PERIPHID4_FOURKB_COUNT_SHIFT
#define PSOC_ETR_PERIPHID4_FOURKB_COUNT_MASK

/* PSOC_ETR_PERIPHID5 */
#define PSOC_ETR_PERIPHID5_PERIPHID5_SHIFT
#define PSOC_ETR_PERIPHID5_PERIPHID5_MASK

/* PSOC_ETR_PERIPHID6 */
#define PSOC_ETR_PERIPHID6_PERIPHID6_SHIFT
#define PSOC_ETR_PERIPHID6_PERIPHID6_MASK

/* PSOC_ETR_PERIPHID7 */
#define PSOC_ETR_PERIPHID7_PERIPHID7_SHIFT
#define PSOC_ETR_PERIPHID7_PERIPHID7_MASK

/* PSOC_ETR_PERIPHID0 */
#define PSOC_ETR_PERIPHID0_PART_NUMBER_BITS7TO0_SHIFT
#define PSOC_ETR_PERIPHID0_PART_NUMBER_BITS7TO0_MASK

/* PSOC_ETR_PERIPHID1 */
#define PSOC_ETR_PERIPHID1_PART_NUMBER_BITS11TO8_SHIFT
#define PSOC_ETR_PERIPHID1_PART_NUMBER_BITS11TO8_MASK
#define PSOC_ETR_PERIPHID1_JEP106_BITS3TO0_SHIFT
#define PSOC_ETR_PERIPHID1_JEP106_BITS3TO0_MASK

/* PSOC_ETR_PERIPHID2 */
#define PSOC_ETR_PERIPHID2_JEP106_BITS6TO4_SHIFT
#define PSOC_ETR_PERIPHID2_JEP106_BITS6TO4_MASK
#define PSOC_ETR_PERIPHID2_JEDEC_SHIFT
#define PSOC_ETR_PERIPHID2_JEDEC_MASK
#define PSOC_ETR_PERIPHID2_REVISION_SHIFT
#define PSOC_ETR_PERIPHID2_REVISION_MASK

/* PSOC_ETR_PERIPHID3 */
#define PSOC_ETR_PERIPHID3_CUSTOMER_MODIFIED_SHIFT
#define PSOC_ETR_PERIPHID3_CUSTOMER_MODIFIED_MASK
#define PSOC_ETR_PERIPHID3_REVAND_SHIFT
#define PSOC_ETR_PERIPHID3_REVAND_MASK

/* PSOC_ETR_COMPID0 */
#define PSOC_ETR_COMPID0_PREAMBLE_SHIFT
#define PSOC_ETR_COMPID0_PREAMBLE_MASK

/* PSOC_ETR_COMPID1 */
#define PSOC_ETR_COMPID1_PREAMBLE_SHIFT
#define PSOC_ETR_COMPID1_PREAMBLE_MASK
#define PSOC_ETR_COMPID1_F_CLASS_SHIFT
#define PSOC_ETR_COMPID1_F_CLASS_MASK

/* PSOC_ETR_COMPID2 */
#define PSOC_ETR_COMPID2_PREAMBLE_SHIFT
#define PSOC_ETR_COMPID2_PREAMBLE_MASK

/* PSOC_ETR_COMPID3 */
#define PSOC_ETR_COMPID3_PREAMBLE_SHIFT
#define PSOC_ETR_COMPID3_PREAMBLE_MASK

#endif /* ASIC_REG_PSOC_ETR_MASKS_H_ */