/* SPDX-License-Identifier: GPL-2.0 * * Copyright 2016-2020 HabanaLabs, Ltd. * All Rights Reserved. * */ /************************************ ** This is an auto-generated file ** ** DO NOT EDIT BELOW ** ************************************/ #ifndef ASIC_REG_NIC0_QPC0_REGS_H_ #define ASIC_REG_NIC0_QPC0_REGS_H_ /* ***************************************** * NIC0_QPC0 * (Prototype: NIC_QPC) ***************************************** */ #define mmNIC0_QPC0_REQ_QPC_CACHE_INVALIDATE … #define mmNIC0_QPC0_REQ_QPC_CACHE_INV_STATUS … #define mmNIC0_QPC0_REQ_STATIC_CONFIG … #define mmNIC0_QPC0_REQ_BASE_ADDRESS_63_32 … #define mmNIC0_QPC0_REQ_BASE_ADDRESS_31_7 … #define mmNIC0_QPC0_REQ_CLEAN_LINK_LIST … #define mmNIC0_QPC0_REQ_ERR_FIFO_PUSH_63_32 … #define mmNIC0_QPC0_REQ_ERR_FIFO_PUSH_31_0 … #define mmNIC0_QPC0_REQ_ERR_QP_STATE_63_32 … #define mmNIC0_QPC0_REQ_ERR_QP_STATE_31_0 … #define mmNIC0_QPC0_RETRY_COUNT_MAX … #define mmNIC0_QPC0_AXI_PROT … #define mmNIC0_QPC0_RES_QPC_CACHE_INVALIDATE … #define mmNIC0_QPC0_RES_QPC_CACHE_INV_STATUS … #define mmNIC0_QPC0_RES_STATIC_CONFIG … #define mmNIC0_QPC0_RES_BASE_ADDRESS_63_32 … #define mmNIC0_QPC0_RES_BASE_ADDRESS_31_7 … #define mmNIC0_QPC0_RES_CLEAN_LINK_LIST … #define mmNIC0_QPC0_ERR_FIFO_WRITE_INDEX … #define mmNIC0_QPC0_ERR_FIFO_PRODUCER_INDEX … #define mmNIC0_QPC0_ERR_FIFO_CONSUMER_INDEX … #define mmNIC0_QPC0_ERR_FIFO_MASK … #define mmNIC0_QPC0_ERR_FIFO_CREDIT … #define mmNIC0_QPC0_ERR_FIFO_CFG … #define mmNIC0_QPC0_ERR_FIFO_INTR_MASK … #define mmNIC0_QPC0_ERR_FIFO_BASE_ADDR_63_32 … #define mmNIC0_QPC0_ERR_FIFO_BASE_ADDR_31_7 … #define mmNIC0_QPC0_GW_BUSY … #define mmNIC0_QPC0_GW_CTRL … #define mmNIC0_QPC0_GW_DATA_0 … #define mmNIC0_QPC0_GW_DATA_1 … #define mmNIC0_QPC0_GW_DATA_2 … #define mmNIC0_QPC0_GW_DATA_3 … #define mmNIC0_QPC0_GW_DATA_4 … #define mmNIC0_QPC0_GW_DATA_5 … #define mmNIC0_QPC0_GW_DATA_6 … #define mmNIC0_QPC0_GW_DATA_7 … #define mmNIC0_QPC0_GW_DATA_8 … #define mmNIC0_QPC0_GW_DATA_9 … #define mmNIC0_QPC0_GW_DATA_10 … #define mmNIC0_QPC0_GW_DATA_11 … #define mmNIC0_QPC0_GW_DATA_12 … #define mmNIC0_QPC0_GW_DATA_13 … #define mmNIC0_QPC0_GW_DATA_14 … #define mmNIC0_QPC0_GW_DATA_15 … #define mmNIC0_QPC0_GW_DATA_16 … #define mmNIC0_QPC0_GW_DATA_17 … #define mmNIC0_QPC0_GW_DATA_18 … #define mmNIC0_QPC0_GW_DATA_19 … #define mmNIC0_QPC0_GW_DATA_20 … #define mmNIC0_QPC0_GW_DATA_21 … #define mmNIC0_QPC0_GW_DATA_22 … #define mmNIC0_QPC0_GW_DATA_23 … #define mmNIC0_QPC0_GW_DATA_24 … #define mmNIC0_QPC0_GW_DATA_25 … #define mmNIC0_QPC0_GW_DATA_26 … #define mmNIC0_QPC0_GW_DATA_27 … #define mmNIC0_QPC0_GW_DATA_28 … #define mmNIC0_QPC0_GW_DATA_29 … #define mmNIC0_QPC0_GW_DATA_30 … #define mmNIC0_QPC0_GW_DATA_31 … #define mmNIC0_QPC0_GW_MASK_0 … #define mmNIC0_QPC0_GW_MASK_1 … #define mmNIC0_QPC0_GW_MASK_2 … #define mmNIC0_QPC0_GW_MASK_3 … #define mmNIC0_QPC0_GW_MASK_4 … #define mmNIC0_QPC0_GW_MASK_5 … #define mmNIC0_QPC0_GW_MASK_6 … #define mmNIC0_QPC0_GW_MASK_7 … #define mmNIC0_QPC0_GW_MASK_8 … #define mmNIC0_QPC0_GW_MASK_9 … #define mmNIC0_QPC0_GW_MASK_10 … #define mmNIC0_QPC0_GW_MASK_11 … #define mmNIC0_QPC0_GW_MASK_12 … #define mmNIC0_QPC0_GW_MASK_13 … #define mmNIC0_QPC0_GW_MASK_14 … #define mmNIC0_QPC0_GW_MASK_15 … #define mmNIC0_QPC0_GW_MASK_16 … #define mmNIC0_QPC0_GW_MASK_17 … #define mmNIC0_QPC0_GW_MASK_18 … #define mmNIC0_QPC0_GW_MASK_19 … #define mmNIC0_QPC0_GW_MASK_20 … #define mmNIC0_QPC0_GW_MASK_21 … #define mmNIC0_QPC0_GW_MASK_22 … #define mmNIC0_QPC0_GW_MASK_23 … #define mmNIC0_QPC0_GW_MASK_24 … #define mmNIC0_QPC0_GW_MASK_25 … #define mmNIC0_QPC0_GW_MASK_26 … #define mmNIC0_QPC0_GW_MASK_27 … #define mmNIC0_QPC0_GW_MASK_28 … #define mmNIC0_QPC0_GW_MASK_29 … #define mmNIC0_QPC0_GW_MASK_30 … #define mmNIC0_QPC0_GW_MASK_31 … #define mmNIC0_QPC0_CC_TIMEOUT … #define mmNIC0_QPC0_CC_WINDOW_INC_EN … #define mmNIC0_QPC0_CC_TICK_WRAP … #define mmNIC0_QPC0_CC_ROLLBACK … #define mmNIC0_QPC0_CC_MAX_WINDOW_SIZE … #define mmNIC0_QPC0_CC_MIN_WINDOW_SIZE … #define mmNIC0_QPC0_CC_ALPHA_LINEAR_0 … #define mmNIC0_QPC0_CC_ALPHA_LINEAR_1 … #define mmNIC0_QPC0_CC_ALPHA_LINEAR_2 … #define mmNIC0_QPC0_CC_ALPHA_LINEAR_3 … #define mmNIC0_QPC0_CC_ALPHA_LINEAR_4 … #define mmNIC0_QPC0_CC_ALPHA_LINEAR_5 … #define mmNIC0_QPC0_CC_ALPHA_LINEAR_6 … #define mmNIC0_QPC0_CC_ALPHA_LINEAR_7 … #define mmNIC0_QPC0_CC_ALPHA_LINEAR_8 … #define mmNIC0_QPC0_CC_ALPHA_LINEAR_9 … #define mmNIC0_QPC0_CC_ALPHA_LINEAR_10 … #define mmNIC0_QPC0_CC_ALPHA_LINEAR_11 … #define mmNIC0_QPC0_CC_ALPHA_LINEAR_12 … #define mmNIC0_QPC0_CC_ALPHA_LINEAR_13 … #define mmNIC0_QPC0_CC_ALPHA_LINEAR_14 … #define mmNIC0_QPC0_CC_ALPHA_LINEAR_15 … #define mmNIC0_QPC0_CC_ALPHA_LOG_0 … #define mmNIC0_QPC0_CC_ALPHA_LOG_1 … #define mmNIC0_QPC0_CC_ALPHA_LOG_2 … #define mmNIC0_QPC0_CC_ALPHA_LOG_3 … #define mmNIC0_QPC0_CC_ALPHA_LOG_4 … #define mmNIC0_QPC0_CC_ALPHA_LOG_5 … #define mmNIC0_QPC0_CC_ALPHA_LOG_6 … #define mmNIC0_QPC0_CC_ALPHA_LOG_7 … #define mmNIC0_QPC0_CC_ALPHA_LOG_8 … #define mmNIC0_QPC0_CC_ALPHA_LOG_9 … #define mmNIC0_QPC0_CC_ALPHA_LOG_10 … #define mmNIC0_QPC0_CC_ALPHA_LOG_11 … #define mmNIC0_QPC0_CC_ALPHA_LOG_12 … #define mmNIC0_QPC0_CC_ALPHA_LOG_13 … #define mmNIC0_QPC0_CC_ALPHA_LOG_14 … #define mmNIC0_QPC0_CC_ALPHA_LOG_15 … #define mmNIC0_QPC0_CC_ALPHA_LOG_THRESHOLD_0 … #define mmNIC0_QPC0_CC_ALPHA_LOG_THRESHOLD_1 … #define mmNIC0_QPC0_CC_ALPHA_LOG_THRESHOLD_2 … #define mmNIC0_QPC0_CC_ALPHA_LOG_THRESHOLD_3 … #define mmNIC0_QPC0_CC_ALPHA_LOG_THRESHOLD_4 … #define mmNIC0_QPC0_CC_ALPHA_LOG_THRESHOLD_5 … #define mmNIC0_QPC0_CC_ALPHA_LOG_THRESHOLD_6 … #define mmNIC0_QPC0_CC_ALPHA_LOG_THRESHOLD_7 … #define mmNIC0_QPC0_CC_ALPHA_LOG_THRESHOLD_8 … #define mmNIC0_QPC0_CC_ALPHA_LOG_THRESHOLD_9 … #define mmNIC0_QPC0_CC_ALPHA_LOG_THRESHOLD_10 … #define mmNIC0_QPC0_CC_ALPHA_LOG_THRESHOLD_11 … #define mmNIC0_QPC0_CC_ALPHA_LOG_THRESHOLD_12 … #define mmNIC0_QPC0_CC_ALPHA_LOG_THRESHOLD_13 … #define mmNIC0_QPC0_CC_ALPHA_LOG_THRESHOLD_14 … #define mmNIC0_QPC0_CC_ALPHA_LOG_THRESHOLD_15 … #define mmNIC0_QPC0_CC_WINDOW_INC_0 … #define mmNIC0_QPC0_CC_WINDOW_INC_1 … #define mmNIC0_QPC0_CC_WINDOW_INC_2 … #define mmNIC0_QPC0_CC_WINDOW_INC_3 … #define mmNIC0_QPC0_CC_WINDOW_INC_4 … #define mmNIC0_QPC0_CC_WINDOW_INC_5 … #define mmNIC0_QPC0_CC_WINDOW_INC_6 … #define mmNIC0_QPC0_CC_WINDOW_INC_7 … #define mmNIC0_QPC0_CC_WINDOW_INC_8 … #define mmNIC0_QPC0_CC_WINDOW_INC_9 … #define mmNIC0_QPC0_CC_WINDOW_INC_10 … #define mmNIC0_QPC0_CC_WINDOW_INC_11 … #define mmNIC0_QPC0_CC_WINDOW_INC_12 … #define mmNIC0_QPC0_CC_WINDOW_INC_13 … #define mmNIC0_QPC0_CC_WINDOW_INC_14 … #define mmNIC0_QPC0_CC_WINDOW_INC_15 … #define mmNIC0_QPC0_CC_WINDOW_IN_THRESHOLD_0 … #define mmNIC0_QPC0_CC_WINDOW_IN_THRESHOLD_1 … #define mmNIC0_QPC0_CC_WINDOW_IN_THRESHOLD_2 … #define mmNIC0_QPC0_CC_WINDOW_IN_THRESHOLD_3 … #define mmNIC0_QPC0_CC_WINDOW_IN_THRESHOLD_4 … #define mmNIC0_QPC0_CC_WINDOW_IN_THRESHOLD_5 … #define mmNIC0_QPC0_CC_WINDOW_IN_THRESHOLD_6 … #define mmNIC0_QPC0_CC_WINDOW_IN_THRESHOLD_7 … #define mmNIC0_QPC0_CC_WINDOW_IN_THRESHOLD_8 … #define mmNIC0_QPC0_CC_WINDOW_IN_THRESHOLD_9 … #define mmNIC0_QPC0_CC_WINDOW_IN_THRESHOLD_10 … #define mmNIC0_QPC0_CC_WINDOW_IN_THRESHOLD_11 … #define mmNIC0_QPC0_CC_WINDOW_IN_THRESHOLD_12 … #define mmNIC0_QPC0_CC_WINDOW_IN_THRESHOLD_13 … #define mmNIC0_QPC0_CC_WINDOW_IN_THRESHOLD_14 … #define mmNIC0_QPC0_CC_WINDOW_IN_THRESHOLD_15 … #define mmNIC0_QPC0_DB_FIFO_USER_OVRD_0 … #define mmNIC0_QPC0_DB_FIFO_USER_OVRD_1 … #define mmNIC0_QPC0_DB_FIFO_USER_OVRD_2 … #define mmNIC0_QPC0_DB_FIFO_USER_OVRD_3 … #define mmNIC0_QPC0_DB_FIFO_USER_OVRD_4 … #define mmNIC0_QPC0_DB_FIFO_USER_OVRD_5 … #define mmNIC0_QPC0_DB_FIFO_USER_OVRD_6 … #define mmNIC0_QPC0_DB_FIFO_USER_OVRD_7 … #define mmNIC0_QPC0_DB_FIFO_USER_OVRD_8 … #define mmNIC0_QPC0_DB_FIFO_USER_OVRD_9 … #define mmNIC0_QPC0_DB_FIFO_USER_OVRD_10 … #define mmNIC0_QPC0_DB_FIFO_USER_OVRD_11 … #define mmNIC0_QPC0_DB_FIFO_USER_OVRD_12 … #define mmNIC0_QPC0_DB_FIFO_USER_OVRD_13 … #define mmNIC0_QPC0_DB_FIFO_USER_OVRD_14 … #define mmNIC0_QPC0_DB_FIFO_USER_OVRD_15 … #define mmNIC0_QPC0_DB_FIFO_USER_OVRD_16 … #define mmNIC0_QPC0_DB_FIFO_USER_OVRD_17 … #define mmNIC0_QPC0_DB_FIFO_USER_OVRD_18 … #define mmNIC0_QPC0_DB_FIFO_USER_OVRD_19 … #define mmNIC0_QPC0_DB_FIFO_USER_OVRD_20 … #define mmNIC0_QPC0_DB_FIFO_USER_OVRD_21 … #define mmNIC0_QPC0_DB_FIFO_USER_OVRD_22 … #define mmNIC0_QPC0_DB_FIFO_USER_OVRD_23 … #define mmNIC0_QPC0_DB_FIFO_USER_OVRD_24 … #define mmNIC0_QPC0_DB_FIFO_USER_OVRD_25 … #define mmNIC0_QPC0_DB_FIFO_USER_OVRD_26 … #define mmNIC0_QPC0_DB_FIFO_USER_OVRD_27 … #define mmNIC0_QPC0_DB_FIFO_USER_OVRD_28 … #define mmNIC0_QPC0_DB_FIFO_USER_OVRD_29 … #define mmNIC0_QPC0_DB_FIFO_USER_OVRD_30 … #define mmNIC0_QPC0_DB_FIFO_USER_OVRD_31 … #define mmNIC0_QPC0_DB_FIFO_CFG_0 … #define mmNIC0_QPC0_DB_FIFO_CFG_1 … #define mmNIC0_QPC0_DB_FIFO_CFG_2 … #define mmNIC0_QPC0_DB_FIFO_CFG_3 … #define mmNIC0_QPC0_DB_FIFO_CFG_4 … #define mmNIC0_QPC0_DB_FIFO_CFG_5 … #define mmNIC0_QPC0_DB_FIFO_CFG_6 … #define mmNIC0_QPC0_DB_FIFO_CFG_7 … #define mmNIC0_QPC0_DB_FIFO_CFG_8 … #define mmNIC0_QPC0_DB_FIFO_CFG_9 … #define mmNIC0_QPC0_DB_FIFO_CFG_10 … #define mmNIC0_QPC0_DB_FIFO_CFG_11 … #define mmNIC0_QPC0_DB_FIFO_CFG_12 … #define mmNIC0_QPC0_DB_FIFO_CFG_13 … #define mmNIC0_QPC0_DB_FIFO_CFG_14 … #define mmNIC0_QPC0_DB_FIFO_CFG_15 … #define mmNIC0_QPC0_DB_FIFO_CFG_16 … #define mmNIC0_QPC0_DB_FIFO_CFG_17 … #define mmNIC0_QPC0_DB_FIFO_CFG_18 … #define mmNIC0_QPC0_DB_FIFO_CFG_19 … #define mmNIC0_QPC0_DB_FIFO_CFG_20 … #define mmNIC0_QPC0_DB_FIFO_CFG_21 … #define mmNIC0_QPC0_DB_FIFO_CFG_22 … #define mmNIC0_QPC0_DB_FIFO_CFG_23 … #define mmNIC0_QPC0_DB_FIFO_CFG_24 … #define mmNIC0_QPC0_DB_FIFO_CFG_25 … #define mmNIC0_QPC0_DB_FIFO_CFG_26 … #define mmNIC0_QPC0_DB_FIFO_CFG_27 … #define mmNIC0_QPC0_DB_FIFO_CFG_28 … #define mmNIC0_QPC0_DB_FIFO_CFG_29 … #define mmNIC0_QPC0_DB_FIFO_CFG_30 … #define mmNIC0_QPC0_DB_FIFO_CFG_31 … #define mmNIC0_QPC0_SECURED_DB_FIRST32 … #define mmNIC0_QPC0_SECURED_DB_SECOND32 … #define mmNIC0_QPC0_SECURED_DB_THIRD32 … #define mmNIC0_QPC0_SECURED_DB_FOURTH32 … #define mmNIC0_QPC0_PRIVILEGE_DB_FIRST32 … #define mmNIC0_QPC0_PRIVILEGE_DB_SECOND32 … #define mmNIC0_QPC0_PRIVILEGE_DB_THIRD32 … #define mmNIC0_QPC0_PRIVILEGE_DB_FOURTH32 … #define mmNIC0_QPC0_DBG_INDICATION … #define mmNIC0_QPC0_WTD_WC_FSM … #define mmNIC0_QPC0_WTD_SLICE_FSM … #define mmNIC0_QPC0_REQ_TX_EMPTY_CNT … #define mmNIC0_QPC0_RES_TX_EMPTY_CNT … #define mmNIC0_QPC0_NUM_ROLLBACKS … #define mmNIC0_QPC0_LAST_QP_ROLLED_BACK … #define mmNIC0_QPC0_NUM_TIMEOUTS … #define mmNIC0_QPC0_LAST_QP_TIMED_OUT … #define mmNIC0_QPC0_WTD_SLICE_FSM_HI … #define mmNIC0_QPC0_INTERRUPT_BASE_0 … #define mmNIC0_QPC0_INTERRUPT_BASE_1 … #define mmNIC0_QPC0_INTERRUPT_BASE_2 … #define mmNIC0_QPC0_INTERRUPT_BASE_3 … #define mmNIC0_QPC0_INTERRUPT_BASE_4 … #define mmNIC0_QPC0_INTERRUPT_BASE_5 … #define mmNIC0_QPC0_INTERRUPT_BASE_6 … #define mmNIC0_QPC0_INTERRUPT_BASE_7 … #define mmNIC0_QPC0_INTERRUPT_BASE_8 … #define mmNIC0_QPC0_INTERRUPT_BASE_9 … #define mmNIC0_QPC0_INTERRUPT_BASE_10 … #define mmNIC0_QPC0_INTERRUPT_DATA_0 … #define mmNIC0_QPC0_INTERRUPT_DATA_1 … #define mmNIC0_QPC0_INTERRUPT_DATA_2 … #define mmNIC0_QPC0_INTERRUPT_DATA_3 … #define mmNIC0_QPC0_INTERRUPT_DATA_4 … #define mmNIC0_QPC0_INTERRUPT_DATA_5 … #define mmNIC0_QPC0_INTERRUPT_DATA_6 … #define mmNIC0_QPC0_INTERRUPT_DATA_7 … #define mmNIC0_QPC0_INTERRUPT_DATA_8 … #define mmNIC0_QPC0_INTERRUPT_DATA_9 … #define mmNIC0_QPC0_INTERRUPT_DATA_10 … #define mmNIC0_QPC0_DBG_COUNT_SELECT_0 … #define mmNIC0_QPC0_DBG_COUNT_SELECT_1 … #define mmNIC0_QPC0_DBG_COUNT_SELECT_2 … #define mmNIC0_QPC0_DBG_COUNT_SELECT_3 … #define mmNIC0_QPC0_DBG_COUNT_SELECT_4 … #define mmNIC0_QPC0_DBG_COUNT_SELECT_5 … #define mmNIC0_QPC0_DBG_COUNT_SELECT_6 … #define mmNIC0_QPC0_DBG_COUNT_SELECT_7 … #define mmNIC0_QPC0_DBG_COUNT_SELECT_8 … #define mmNIC0_QPC0_DBG_COUNT_SELECT_9 … #define mmNIC0_QPC0_DBG_COUNT_SELECT_10 … #define mmNIC0_QPC0_DBG_COUNT_SELECT_11 … #define mmNIC0_QPC0_DOORBELL_SECURITY … #define mmNIC0_QPC0_DBG_CFG … #define mmNIC0_QPC0_RES_RING0_PI … #define mmNIC0_QPC0_RES_RING0_CI … #define mmNIC0_QPC0_RES_RING0_CFG … #define mmNIC0_QPC0_RES_RING1_PI … #define mmNIC0_QPC0_RES_RING1_CI … #define mmNIC0_QPC0_RES_RING1_CFG … #define mmNIC0_QPC0_RES_RING2_PI … #define mmNIC0_QPC0_RES_RING2_CI … #define mmNIC0_QPC0_RES_RING2_CFG … #define mmNIC0_QPC0_RES_RING3_PI … #define mmNIC0_QPC0_RES_RING3_CI … #define mmNIC0_QPC0_RES_RING3_CFG … #define mmNIC0_QPC0_REQ_RING0_CI … #define mmNIC0_QPC0_REQ_RING1_CI … #define mmNIC0_QPC0_REQ_RING2_CI … #define mmNIC0_QPC0_REQ_RING3_CI … #define mmNIC0_QPC0_INTERRUPT_CAUSE … #define mmNIC0_QPC0_INTERRUPT_MASK … #define mmNIC0_QPC0_INTERRUPT_CLR … #define mmNIC0_QPC0_INTERRUPT_EN … #define mmNIC0_QPC0_INTERRUPT_CFG … #define mmNIC0_QPC0_INTERRUPT_RESP_ERR_CAUSE … #define mmNIC0_QPC0_INTERRUPT_RESP_ERR_MASK … #define mmNIC0_QPC0_INTERRUPR_RESP_ERR_CLR … #define mmNIC0_QPC0_TMR_GW_VALID … #define mmNIC0_QPC0_TMR_GW_DATA0 … #define mmNIC0_QPC0_TMR_GW_DATA1 … #define mmNIC0_QPC0_RNR_RETRY_COUNT_EN … #define mmNIC0_QPC0_EVENT_QUE_BASE_ADDR_63_32 … #define mmNIC0_QPC0_EVENT_QUE_BASE_ADDR_31_7 … #define mmNIC0_QPC0_EVENT_QUE_LOG_SIZE … #define mmNIC0_QPC0_EVENT_QUE_WRITE_INDEX … #define mmNIC0_QPC0_EVENT_QUE_PRODUCER_INDEX … #define mmNIC0_QPC0_EVENT_QUE_PI_ADDR_63_32 … #define mmNIC0_QPC0_EVENT_QUE_PI_ADDR_31_7 … #define mmNIC0_QPC0_EVENT_QUE_CONSUMER_INDEX_CB … #define mmNIC0_QPC0_EVENT_QUE_CFG … #define mmNIC0_QPC0_LBW_PROT … #define mmNIC0_QPC0_MEM_WRITE_INIT … #define mmNIC0_QPC0_QMAN_DOORBELL … #define mmNIC0_QPC0_QMAN_DOORBELL_QPN … #define mmNIC0_QPC0_SECURED_CQ_NUMBER … #define mmNIC0_QPC0_SECURED_CQ_CONSUMER_INDEX … #define mmNIC0_QPC0_PRIVILEGE_CQ_NUMBER … #define mmNIC0_QPC0_PRIVILEGE_CQ_CONSUMER_INDEX … #define mmNIC0_QPC0_TX_WQ_BASE_ADDR_63_32_0 … #define mmNIC0_QPC0_TX_WQ_BASE_ADDR_63_32_1 … #define mmNIC0_QPC0_TX_WQ_BASE_ADDR_63_32_2 … #define mmNIC0_QPC0_TX_WQ_BASE_ADDR_63_32_3 … #define mmNIC0_QPC0_TX_WQ_BASE_ADDR_31_0_0 … #define mmNIC0_QPC0_TX_WQ_BASE_ADDR_31_0_1 … #define mmNIC0_QPC0_TX_WQ_BASE_ADDR_31_0_2 … #define mmNIC0_QPC0_TX_WQ_BASE_ADDR_31_0_3 … #define mmNIC0_QPC0_LOG_MAX_TX_WQ_SIZE_0 … #define mmNIC0_QPC0_LOG_MAX_TX_WQ_SIZE_1 … #define mmNIC0_QPC0_LOG_MAX_TX_WQ_SIZE_2 … #define mmNIC0_QPC0_LOG_MAX_TX_WQ_SIZE_3 … #define mmNIC0_QPC0_MMU_BYPASS_TX_WQ_0 … #define mmNIC0_QPC0_MMU_BYPASS_TX_WQ_1 … #define mmNIC0_QPC0_MMU_BYPASS_TX_WQ_2 … #define mmNIC0_QPC0_MMU_BYPASS_TX_WQ_3 … #define mmNIC0_QPC0_RX_WQ_BASE_ADDR_63_32_0 … #define mmNIC0_QPC0_RX_WQ_BASE_ADDR_63_32_1 … #define mmNIC0_QPC0_RX_WQ_BASE_ADDR_63_32_2 … #define mmNIC0_QPC0_RX_WQ_BASE_ADDR_63_32_3 … #define mmNIC0_QPC0_RX_WQ_BASE_ADDR_31_0_0 … #define mmNIC0_QPC0_RX_WQ_BASE_ADDR_31_0_1 … #define mmNIC0_QPC0_RX_WQ_BASE_ADDR_31_0_2 … #define mmNIC0_QPC0_RX_WQ_BASE_ADDR_31_0_3 … #define mmNIC0_QPC0_LOG_MAX_RX_WQ_SIZE_0 … #define mmNIC0_QPC0_LOG_MAX_RX_WQ_SIZE_1 … #define mmNIC0_QPC0_LOG_MAX_RX_WQ_SIZE_2 … #define mmNIC0_QPC0_LOG_MAX_RX_WQ_SIZE_3 … #define mmNIC0_QPC0_MMU_BYPASS_RX_WQ_0 … #define mmNIC0_QPC0_MMU_BYPASS_RX_WQ_1 … #define mmNIC0_QPC0_MMU_BYPASS_RX_WQ_2 … #define mmNIC0_QPC0_MMU_BYPASS_RX_WQ_3 … #define mmNIC0_QPC0_WQE_MEM_WRITE_AXI_PROT … #define mmNIC0_QPC0_WQ_UPPER_THRESHOLD … #define mmNIC0_QPC0_WQ_LOWER_THRESHOLD … #define mmNIC0_QPC0_WQ_BP_2ARC_ADDR … #define mmNIC0_QPC0_WQ_BP_2QMAN_ADDR … #define mmNIC0_QPC0_WTD_CONFIG … #define mmNIC0_QPC0_REQTX_ERR_FIFO_PUSH_63_32 … #define mmNIC0_QPC0_REQTX_ERR_FIFO_PUSH_31_0 … #define mmNIC0_QPC0_REQTX_ERR_QP_STATE_63_32 … #define mmNIC0_QPC0_REQTX_ERR_QP_STATE_31_0 … #define mmNIC0_QPC0_EVENT_QUE_CONSUMER_INDEX … #define mmNIC0_QPC0_ARM_CQ_NUM … #define mmNIC0_QPC0_ARM_CQ_INDEX … #define mmNIC0_QPC0_QPC_CLOCK_GATE … #define mmNIC0_QPC0_QPC_CLOCK_GATE_DIS … #define mmNIC0_QPC0_CONG_QUE_BASE_ADDR_63_32 … #define mmNIC0_QPC0_CONG_QUE_BASE_ADDR_31_7 … #define mmNIC0_QPC0_CONG_QUE_LOG_SIZE … #define mmNIC0_QPC0_CONG_QUE_WRITE_INDEX … #define mmNIC0_QPC0_CONG_QUE_PRODUCER_INDEX … #define mmNIC0_QPC0_CONG_QUE_PI_ADDR_63_32 … #define mmNIC0_QPC0_CONG_QUE_PI_ADDR_31_7 … #define mmNIC0_QPC0_CONG_QUE_CONSUMER_INDEX_CB … #define mmNIC0_QPC0_CONG_QUE_CFG … #define mmNIC0_QPC0_CONG_QUE_CONSUMER_INDEX … #define mmNIC0_QPC0_LINEAR_WQE_STATIC_0 … #define mmNIC0_QPC0_LINEAR_WQE_STATIC_1 … #define mmNIC0_QPC0_LINEAR_WQE_STATIC_2 … #define mmNIC0_QPC0_LINEAR_WQE_STATIC_3 … #define mmNIC0_QPC0_LINEAR_WQE_STATIC_4 … #define mmNIC0_QPC0_LINEAR_WQE_STATIC_5 … #define mmNIC0_QPC0_LINEAR_WQE_STATIC_6 … #define mmNIC0_QPC0_LINEAR_WQE_STATIC_7 … #define mmNIC0_QPC0_LINEAR_WQE_STATIC_8 … #define mmNIC0_QPC0_LINEAR_WQE_STATIC_9 … #define mmNIC0_QPC0_LINEAR_WQE_DYNAMIC_0 … #define mmNIC0_QPC0_LINEAR_WQE_DYNAMIC_1 … #define mmNIC0_QPC0_LINEAR_WQE_DYNAMIC_2 … #define mmNIC0_QPC0_LINEAR_WQE_DYNAMIC_3 … #define mmNIC0_QPC0_LINEAR_WQE_DYNAMIC_4 … #define mmNIC0_QPC0_LINEAR_WQE_DYNAMIC_5 … #define mmNIC0_QPC0_LINEAR_WQE_QPN … #define mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_0 … #define mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_1 … #define mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_2 … #define mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_3 … #define mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_4 … #define mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_5 … #define mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_6 … #define mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_7 … #define mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_8 … #define mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_9 … #define mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_10 … #define mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_11 … #define mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_12 … #define mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_13 … #define mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_14 … #define mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_15 … #define mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_16 … #define mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_17 … #define mmNIC0_QPC0_MULTI_STRIDE_WQE_DYNAMIC_0 … #define mmNIC0_QPC0_MULTI_STRIDE_WQE_DYNAMIC_1 … #define mmNIC0_QPC0_MULTI_STRIDE_WQE_DYNAMIC_2 … #define mmNIC0_QPC0_MULTI_STRIDE_WQE_DYNAMIC_3 … #define mmNIC0_QPC0_MULTI_STRIDE_WQE_DYNAMIC_4 … #define mmNIC0_QPC0_MULTI_STRIDE_WQE_DYNAMIC_5 … #define mmNIC0_QPC0_MULTI_STRIDE_WQE_QPN … #endif /* ASIC_REG_NIC0_QPC0_REGS_H_ */
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